Analog Devices ADuCM355 2024.06.03 ARM Cortex-CM3 Microcontroller based device CM3 r0p1 little 3 false 8 32 AFE Unknown AFE 0x0 0x0 0x800 registers n AFE_ERROR AFE_ERROR 47 AFE_ADC AFE_ADC 48 AFE_GEN AFE_GEN 49 AFE_CMDFIFO AFE_CMDFIFO 50 AFE_DATAFIFO AFE_DATAFIFO 51 AFE_Watchdog AFE_Watchdog 52 AFE_CRC AFE_CRC 53 AFE_GPT0 AFE_GPT0 54 AFE_GPT1 AFE_GPT1 55 ADCBUFCON Configure ADC Input Buffer 0x38C 32 read-write n 0x0 0x0 AMPDIS Disable OpAmp. 4 5 read-write CHOPDIS Disable Chop 0 4 read-write ADCCON ADC Configuration 0x1A8 32 read-write n 0x0 0x0 GNOFFSEL Obsolete 13 2 read-write GNOFSELPGA Internal Offset/Gain Cancellation 15 1 read-write GNPGA PGA Gain Setup 16 3 read-write MUXSELN Select Negative Input 8 5 read-write MUXSELP Select Positive Input 0 6 read-write ADCDAT ADC Raw Result 0x74 32 read-write n 0x0 0x0 DATA ADC Result 0 16 read-write ADCDELTA ADC Delta Value 0xB8 32 read-write n 0x0 0x0 DELTAVAL ADCDAT Code Differences Limit Option 0 16 read-write ADCFILTERCON ADC Output Filters Configuration 0x44 32 read-write n 0x0 0x0 ADCCLK ADC Data Rate 0 1 read-write AVRGEN Average Function Enable 7 1 read-write AVRGNUM Number of Samples Averaged 14 2 read-write DACWAVECLKENB DAC Wave Clock Enable 17 1 read-write DFTCLKENB DFT Clock Enable 18 1 read-write LPFBYPEN 50/60Hz Low Pass Filter 4 1 read-write SINC2CLKENB SINC2 Filter Clock Enable 16 1 read-write SINC2OSR SINC2 OSR 8 4 read-write SINC3BYP SINC3 Filter Bypass 6 1 read-write SINC3OSR SINC3 OSR 12 2 read-write ADCGAINGN1 ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel 0x240 32 read-write n 0x0 0x0 VALUE Gain Calibration PGA Gain 1x 0 15 read-write ADCGAINGN1P5 ADC Gain Calibration Auxiliary Input Channel (PGA Gain=1.5) 0x270 32 read-write n 0x0 0x0 VALUE Gain Calibration PGA Gain 1.5x 0 15 read-write ADCGAINGN2 ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2) 0x274 32 read-write n 0x0 0x0 VALUE Gain Calibration PGA Gain 2x 0 15 read-write ADCGAINGN4 ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4) 0x278 32 read-write n 0x0 0x0 VALUE Gain Calibration PGA Gain 4x 0 15 read-write ADCGAINGN9 ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9) 0x298 32 read-write n 0x0 0x0 VALUE Gain Calibration PGA Gain 9x 0 15 read-write ADCGAINTEMPSENS0 ADC Gain Calibration Temp Sensor Channel 0x238 32 read-write n 0x0 0x0 VALUE Gain Calibration Temp Sensor Channel 0 15 read-write ADCGAINTEMPSENS1 ADC Gain Calibration Temperature Sensor Channel 0x2AC 32 read-write n 0x0 0x0 VALUE Gain Calibration for Diode Temp Sensor 0 15 read-write ADCGNHSTIA ADC Gain Calibration for HS TIA Channel 0x284 32 read-write n 0x0 0x0 VALUE Gain Error Calibration HS TIA Channel 0 15 read-write ADCGNLPTIA0 ADC GAIN Calibration for LP TIA0 Channel 0x28C 32 read-write n 0x0 0x0 VALUE Gain Error Calibration ULPTIA0 0 15 read-write ADCGNLPTIA1 ADC GAIN Calibration for LP TIA1 Channel 0x2C4 32 read-write n 0x0 0x0 ULPTIA1GN Gain Calibration ULP-TIA1 0 15 read-write ADCINTIEN ADC Interrupt Enable Register 0x88 32 read-write n 0x0 0x0 ADCDELTAFAILIEN Delta Interrupt 6 1 read-write ADCMAXFAILIEN ADCMAX Interrupt 5 1 read-write ADCMINFAILIEN ADCMIN Interrupt 4 1 read-write ADCRDYIEN ADCDAT Ready Interrupt 0 1 read-write DFTRDYIEN DFT Result Ready Interrupt 1 1 read-write MEANIEN Mean Interrupt 7 1 read-write SINC2RDYIEN Low Pass Filter Result Interrupt 2 1 read-write TEMPRDYIEN Temp Sensor Interrupt 3 1 read-write VARIEN Variance Interrupt 8 1 read-write ADCINTSTA ADC Interrupt Status 0x98 32 read-write n 0x0 0x0 ADCDIFFERR ADC Delta Ready 6 1 read-write ADCMAXERR ADC Maximum Value 5 1 read-write ADCMINERR ADC Minimum Value 4 1 read-write ADCRDY ADC Result Ready Status 0 1 read-write DFTRDY DFT Result Ready Status 1 1 read-write MEANRDY Mean Result Ready 7 1 read-write SINC2RDY Low Pass Filter Result Status 2 1 read-write TEMPRDY Temp Sensor Result Ready 3 1 read-write VARRDY Variance Result Ready 8 1 read-write ADCMAX ADC Maximum Value Check 0xB0 32 read-write n 0x0 0x0 MAXVAL ADC Max Threshold 0 16 read-write ADCMAXSMEN ADCMAX Hysteresis Value 0xB4 32 read-write n 0x0 0x0 MAXSWEN ADCMAX Hysteresis Value 0 16 read-write ADCMIN ADC Minimum Value Check 0xA8 32 read-write n 0x0 0x0 MINVAL ADC Minimum Value Threshold 0 16 read-write ADCMINSM ADCMIN Hysteresis Value 0xAC 32 read-write n 0x0 0x0 MINCLRVAL ADCMIN Hysteresis Value 0 16 read-write ADCOFFSETEMPSENS1 ADC Offset Calibration Temp Sensor Channel 1 0x2A8 32 read-write n 0x0 0x0 VALUE Offset Calibration Temp Sensor 0 15 read-write ADCOFFSETGN1 ADC Offset Calibration Auxiliary Channel (PGA Gain=1) 0x244 32 read-write n 0x0 0x0 VALUE Offset Calibration Gain1 0 15 read-write ADCOFFSETGN1P5 Offset Calibration Auxiliary Channel (PGA Gain =1.5) 0x2CC 32 read-write n 0x0 0x0 VALUE Offset Calibration Gain1.5 0 15 read-write ADCOFFSETGN2 Offset Calibration Auxiliary Channel (PGA Gain =2) 0x2C8 32 read-write n 0x0 0x0 VALUE Offset Calibration Auxiliary Channel (PGA Gain =2) 0 15 read-write ADCOFFSETGN4 Offset Calibration Auxiliary Channel (PGA Gain =4) 0x2D4 32 read-write n 0x0 0x0 VALUE Offset Calibration Gain4 0 15 read-write ADCOFFSETGN9 Offset Calibration Auxiliary Channel (PGA Gain =9) 0x2D0 32 read-write n 0x0 0x0 VALUE Offset Calibration Gain9 0 15 read-write ADCOFFSETHSTIA ADC Offset Calibration High Speed TIA Channel 0x234 32 read-write n 0x0 0x0 VALUE HPTIA Offset Calibration 0 15 read-write ADCOFFSETLPTIA0 ADC Offset Calibration ULP-TIA0 Channel 0x288 32 read-write n 0x0 0x0 VALUE Offset Calibration for ULP-TIA0 0 15 read-write ADCOFFSETLPTIA1 ADC Offset Calibration LP TIA1 Channel 0x2C0 32 read-write n 0x0 0x0 VALUE Offset Calibration for ULP-TIA1 0 15 read-write ADCOFFSETTEMPSENS0 ADC Offset Calibration Temp Sensor Channel 0 0x23C 32 read-write n 0x0 0x0 VALUE Offset Calibration Temp Sensor 0 15 read-write ADCPGAGN4OFCAL ADC Gain Calibration with DC Cancellation(PGA G=4) 0x294 32 read-write n 0x0 0x0 ADCGAINAUX DC Calibration Gain=4 0 15 read-write ADCPGAOFFSETCANCEL ADC Offset Cancellation (Optional) 0x280 32 read-write n 0x0 0x0 OFFSETCANCEL Offset Cancellation 0 15 read-write AFECON AFE Configuration 0x0 32 read-write n 0x0 0x0 ADCCONVEN ADC Conversion Start Enable 8 1 read-write ADCEN ADC Power Enable 7 1 read-write ALDOILIMITEN Analog LDO Current Limiting Enable 19 1 read-write DACBUFEN Enable DC DAC Buffer 21 1 read-write DACEN High Power DAC Enable 6 1 read-write Off High Power DAC Disabled 0 On High Power DAC Enabled 1 DACREFEN High Speed DAC Reference Enable 20 1 read-write DFTEN DFT Hardware Accelerator Enable 15 1 read-write EXBUFEN Enable Excitation Buffer 9 1 read-write HPREFDIS Disable High Power Reference 5 1 read-write INAMPEN Enable Excitation Amplifier 10 1 read-write SINC2EN ADC Output 50/60Hz Filter Enable 16 1 read-write TEMPCONVEN ADC Temp Sensor Convert Enable 13 1 read-write TEMPSENSEN0 ADC Temperature Sensor Channel Enable 12 1 read-write TIAEN High Power TIA Enable 11 1 read-write WAVEGENEN Waveform Generator Enable 14 1 read-write AFEGENINTSTA Analog Generation Interrupt 0x9C 32 read-write n 0x0 0x0 CUSTOMIRQ0 Custom IRQ 0 0 1 read-write CUSTOMIRQ1 Custom IRQ 1. 1 1 read-write CUSTOMIRQ2 Custom IRQ 2 2 1 read-write CUSTOMIRQ3 Custom IRQ 3. 3 1 read-write BUFSENCON HP and LP Buffer Control 0x180 32 read-write n 0x0 0x0 V1P1HPADCEN Enable 1.1V HP CM Buffer 4 1 read-write Off Disable 1.1V HP Common Mode Buffer 0 On Enable 1.1V HP Common Mode Buffer 1 V1P1LPADCCHGDIS Controls Decoupling Cap Discharge Switch 6 1 read-write EnChrg Open switch 0 DisChrg Close Switch 1 V1P1LPADCEN ADC 1.1V LP Buffer 5 1 read-write Disable Disable ADC 1.8V LP Reference Buffer 0 Enable Enable ADC 1.8V LP Reference Buffer 1 V1P8HPADCCHGDIS Controls Decoupling Cap Discharge Switch 3 1 read-write Open Open switch 0 Closed Close Switch 1 V1P8HPADCEN HP 1.8V Reference Buffer 0 1 read-write HPBUF_DIS Disable 1.8V HP ADC Reference Buffer 0 HPBUF_EN Enable 1.8V HP ADC Reference Buffer 1 V1P8HPADCILIMITEN HP ADC Input Current Limit 1 1 read-write Limit_Dis Disable buffer Current Limit 0 Limit_En Enable buffer Current Limit 1 V1P8LPADCEN ADC 1.8V LP Reference Buffer 2 1 read-write LPADCREF_DIS Disable LP 1.8V Reference Buffer 0 LPADCREF_EN Enable LP 1.8V Reference Buffer 1 V1P8THERMSTEN Buffered Reference Output 8 1 read-write DIS Disable 1.8V Buffered Reference output 0 EN Enable 1.8V Buffered Reference output 1 CALDATLOCK Calibration Data Lock 0x230 32 read-write n 0x0 0x0 KEY Password for Calibration Data Registers 0 32 read-write DACDCBUFCON DAC DC Buffer Configuration 0x104 32 read-write n 0x0 0x0 CHANSEL DAC DC Channel Selection 1 1 read-write Chan0 ULPDAC0 Sets DC level 0 Chan1 ULPDAC1 Sets DC level 1 Reserved_0 Reserved 0 1 read-write DACGAIN DACGAIN 0x260 32 read-write n 0x0 0x0 VALUE HS DAC Gain Correction Factor 0 12 read-write DACOFFSET DAC Offset with Attenuator Disabled (LP Mode) 0x268 32 read-write n 0x0 0x0 VALUE DAC Offset Correction Factor 0 12 read-write DACOFFSETATTEN DAC Offset with Attenuator Enabled (LP Mode) 0x264 32 read-write n 0x0 0x0 VALUE DAC Offset Correction Factor 0 12 read-write DACOFFSETATTENHP DAC Offset with Attenuator Enabled (HP Mode) 0x2B8 32 read-write n 0x0 0x0 VALUE DAC Offset Correction Factor 0 12 read-write DACOFFSETHP DAC Offset with Attenuator Disabled (HP Mode) 0x2BC 32 read-write n 0x0 0x0 VALUE DAC Offset Correction Factor 0 12 read-write DE0RESCON DE0 HSTIA Resistors Configuration 0xF8 32 read-write n 0x0 0x0 DE0RCON DE0 RLOAD RTIA Setting 0 8 read-write DE1RESCON DE1 HSTIA Resistors Configuration 0xF4 32 read-write n 0x0 0x0 DE1RCON DE1 RLOAD RTIA Setting 0 8 read-write DFTCON AFE DSP Configuration 0xD0 32 read-write n 0x0 0x0 DFTINSEL DFT Input Select 20 2 read-write DFTNUM ADC Samples Used 4 4 read-write HANNINGEN Hanning Window Enable 0 1 read-write DFTIMAG DFT Result, Imaginary Part 0x7C 32 read-write n 0x0 0x0 DATA DFT Imaginary 0 18 read-write DFTREAL DFT Result, Real Part 0x78 32 read-write n 0x0 0x0 DATA DFT Real 0 18 read-write DSWFULLCON Switch Matrix Full Configuration (D) 0x150 32 read-write n 0x0 0x0 D2 Control of D2 Switch. 1 1 read-write D3 Control of D3 Switch. 2 1 read-write D4 Control of D4 Switch. 3 1 read-write D5 Control of D5 Switch. 4 1 read-write D6 Control of D6 Switch. 5 1 read-write D7 Control of D7 Switch. 6 1 read-write D8 Control of D8 Switch. 7 1 read-write DR0 Control of Dr0 Switch. 0 1 read-write DSWSTA Switch Matrix Status (D) 0x1B0 32 read-write n 0x0 0x0 D1STA Status of Dr0 Switch. 0 1 read-only D2STA Status of D2 Switch. 1 1 read-only D3STA Status of D3 Switch. 2 1 read-only D4STA Status of D4 Switch. 3 1 read-only D5STA Status of D5 Switch. 4 1 read-only D6STA Status of D6 Switch. 5 1 read-only D7STA Status of D7 Switch. 6 1 read-only D8STA Status of D8 Switch. 7 1 read-only HPOSCCON HPOSC Configuration 0xBC 32 read-write n 0x0 0x0 CLK32MHZEN 16M/32M Output Selector Signal. 2 1 read-write HSDACCON High Speed DAC Configuration 0x10 32 read-write n 0x0 0x0 ATTENEN PGA Stage Gain Attenuation 0 1 read-write INAMPGNMDE Excitation Amplifier Gain Control 12 1 read-write RATE DAC Update Rate 1 8 read-write HSDACDAT HS DAC Code 0x48 32 read-write n 0x0 0x0 DACDAT DAC Code 0 12 read-write HSRTIACON High Power RTIA Configuration 0xF0 32 read-write n 0x0 0x0 CTIACON Configure Capacitor in Parallel with RTIA 5 8 read-write RTIACON Configure General RTIA Value 0 4 read-write TIASW6CON SW6 Control 4 1 read-write HSTIACON HSTIA Amplifier Configuration 0xFC 32 read-write n 0x0 0x0 VBIASSEL Select HSTIA Positive Input 0 2 read-write LPDACCON0 LPDAC Control Bits 0x128 32 read-write n 0x0 0x0 DACMDE LPDAC0 Switch Settings 5 1 read-write NORM ULPDAC0 switches set for normal mode 0 DIAG ULPDAC0 switches set for Diagnostic mode 1 PWDEN LPDAC0 Power Down 1 1 read-write PWREN ULPDAC0 Powered On 0 PWRDIS ULPDAC0 Powered Off 1 REFSEL Reference Select Bit 2 1 read-write ULPREF ULP2P5V Ref 0 AVDD AVDD Reference 1 RSTEN Enable Writes to ULPDAC0 0 1 read-write WRITEDIS Disable ULPDAC0 Writes 0 WRITEEN Enable ULPDAC0 Writes 1 VBIASMUX VBIAS MUX Select 3 1 read-write 12BIT Output 12Bit 0 EN output 6Bit 1 VZEROMUX VZERO MUX Select 4 1 read-write BITS6 VZERO 6BIT 0 BITS12 VZERO 12BIT 1 WAVETYPE LPDAC Data Source 6 1 read-write MMR Direct from ULPDACDAT0 0 WAVEGEN Waveform generator 1 LPDACCON1 ULP_DACCON1 0x134 32 read-write n 0x0 0x0 DACMDE LPDAC1 Switch Settings 5 1 read-write NORM ULPDAC1 switches set for normal mode 0 DIAG ULPDAC1 switches set for Diagnostic mode 1 PWDEN ULPDAC0 Power 1 1 read-write PWREN ULPDAC1 Powered On 0 PWRDIS ULPDAC1 Powered Off 1 REFSEL REFSEL 2 1 read-write ULPREF Unknown 0 AVDD Unknown 1 RSTEN Enable Writes to ULPDAC1 0 1 read-write WRITEDIS Disable ULPDAC1 Writes 0 WRITEEN Enable ULPDAC1 Writes 1 VBIASMUX BITSEL 3 1 read-write DIS 12BIT Output 0 EN 6BIT Output 1 VZEROMUX VZEROOUT 4 1 read-write BITS6 VZERO 6BIT 0 BITS12 VZERO 12BIT 1 WAVETYPE DAC Input Source 6 1 read-write LPDACDAT0 LPDAC Data-out 0x120 32 read-write n 0x0 0x0 DACIN12 12BITVAL, 1LSB=537uV 0 12 read-write DACIN6 6BITVAL, 1LSB=34.375mV 12 6 read-write LPDACDAT1 Low Power DAC1 data register 0x12C 32 read-write n 0x0 0x0 DACIN12 12BITVAL, 1LSB=537uV 0 12 read-write DACIN6 6BITVAL, 1LSB=34.375mV 12 6 read-write LPDACSW0 LPDAC0 Switch Control 0x124 32 read-write n 0x0 0x0 LPDACSW LPDAC0 Switches Matrix 0 5 read-write LPMODEDIS Switch Control 5 1 read-write DACCONBIT5 ULPDAC Switch controlled by ULPDACCON0 bit 5 0 OVRRIDE ULPDAC Switches override 1 LPDACSW1 Control register for switches to LPDAC1 0x130 32 read-write n 0x0 0x0 LPDACSW ULPDAC0 Switches Matrix 0 5 read-write LPMODEDIS Switch Control 5 1 read-write DACCONBIT5 ULPDAC Switch controlled by ULPDACCON1 bit 5 0 OVRRIDE ULPDAC Switches override 1 LPREFBUFCON LPREF_BUF_CON 0x50 32 read-write n 0x0 0x0 BOOSTCURRENT Set: Drive 2 Dac Unset Drive 1 Dac, and Save Power 2 1 read-write LPBUF2P5DIS Low Power Bandgap's Output Buffer 1 1 read-write LPREFDIS Set This Bit Will Power Down Low Power Bandgap 0 1 read-write LPTIACON0 ULPTIA Control Bits Channel 0 0xEC 32 read-write n 0x0 0x0 CHOPEN Chopping Enable 16 2 read-write HALFPWR Half Power Mode Select 2 1 read-write IBOOST Current Boost Control 3 2 read-write PAPDEN PA Power Down 1 1 read-write TIAGAIN Set RTIA 5 5 read-write DISCONTIA Disconnect TIA Gain resistor 0 TIAGAIN200 200 Ohm 1 TIAGAIN16k 16k 10 TIAGAIN20k 20k 11 TIAGAIN24k 24k 12 TIAGAIN30k 30k 13 TIAGAIN32k 32k 14 TIAGAIN40k 40k 15 TIAGAIN48k 48k 16 TIAGAIN64k 64k 17 TIAGAIN85k 85k 18 TIAGAIN96k 96k 19 TIAGAIN1k 1k ohm 2 TIAGAIN100k 100k 20 TIAGAIN120k 120k 21 TIAGAIN128k 128k 22 TIAGAIN160k 160k 23 TIAGAIN196k 196k 24 TIAGAIN256k 256k 25 TIAGAIN512k 512k 26 TIAGAIN2k 2k 3 TIAGAIN3k 3k 4 TIAGAIN4k 4k 5 TIAGAIN6k 6k 6 TIAGAIN8k 8k 7 TIAGAIN10k 10k 8 TIAGAIN12k 12k 9 TIAPDEN TIA Power Down 0 1 read-write TIARF Set LPF Resistor 13 3 read-write DISCONRF Disconnect TIA output from LPF pin 0 BYPRF Bypass resistor 1 RF20k 20k Ohm 2 RF100k 100k Ohm 3 RF200k 200k Ohm 4 RF400k 400k Ohm 5 RF600k 600k Ohm 6 RF1MOHM 1Meg Ohm 7 TIARL Set RLOAD 10 3 read-write RL0 0 ohm 0 RL10 10 ohm 1 RL30 30 ohm 2 RL50 50 ohm 3 RL100 100 ohm 4 RL1p6k 1.6kohm 5 RL3p1k 3.1kohm 6 RL3p5k 3.6kohm 7 LPTIACON1 ULPTIA Control Bits Channel 1 0xE8 32 read-write n 0x0 0x0 CHOPEN Chopping Enable 16 2 read-write HALFPWR Half Power Mode Select 2 1 read-write IBOOST Current Boost Control 3 2 read-write PAPDEN PA Power Down 1 1 read-write TIAGAIN Set RTIA Gain Resistor 5 5 read-write DISCONTIA Disconnect TIA Gain resistor 0 TIAGAIN200 200 Ohm 1 TIAGAIN16k 16k 10 TIAGAIN20k 20k 11 TIAGAIN24k 24k 12 TIAGAIN30k 30k 13 TIAGAIN32k 32k 14 TIAGAIN40k 40k 15 TIAGAIN48k 48k 16 TIAGAIN64k 64k 17 TIAGAIN85k 85k 18 TIAGAIN96k 96k 19 TIAGAIN1k 1k ohm 2 TIAGAIN100k 100k 20 TIAGAIN120k 120k 21 TIAGAIN128k 128k 22 TIAGAIN160k 160k 23 TIAGAIN196k 196k 24 TIAGAIN256k 256k 25 TIAGAIN512k 512k 26 TIAGAIN2k 2k 3 TIAGAIN3k 3k 4 TIAGAIN4k 4k 5 TIAGAIN6k 6k 6 TIAGAIN8k 8k 7 TIAGAIN10k 10k 8 TIAGAIN12k 12k 9 TIAPDEN TIA Power Down 0 1 read-write TIARF Set LPF Resistor 13 3 read-write DISCONRF Disconnect TIA output from LPF pin 0 BYPRF Bypass resistor 1 RF20k 20k Ohm 2 RF100k 100k Ohm 3 RF200k 200k Ohm 4 RF400k 400k Ohm 5 RF600k 600k Ohm 6 RF1MOHM 1Meg Ohm 7 TIARL Set RLOAD 10 3 read-write RL0 0 ohm 0 RL10 10 ohm 1 RL30 30 ohm 2 RL50 50 ohm 3 RL100 100 ohm 4 RL1p6k 1.6kohm 5 RL3p1k 3.1kohm 6 RL3p5k 3.6kohm 7 LPTIASW0 ULPTIA Switch Configuration for Channel 0 0xE4 32 read-write n 0x0 0x0 PABIASSEL TIA SW12 Control. Active High 12 1 read-write RECAL TIA SW15 Control. Active High 15 1 read-write TIABIASSEL TIA SW13 Control. Active High 13 1 read-write TIASWCON TIA SW[11:0] Control 0 12 read-write LOWNOISE Work mode, vzero-vbias=0. 108 11 CAPA test with LP TIA 20 NORM Normal work mode 44 DIO Normal work mode with back-back diode enabled. 45 SHORTSW Work mode with short switch protection 46 VZEROSHARE TIA SW14 Control. Active High 14 1 read-write LPTIASW1 ULPTIA Switch Configuration for Channel 1 0xE0 32 read-write n 0x0 0x0 PABIASSEL TIA SW12 Control. Active High 12 1 read-write TIABIASSEL TIA SW13 Control. Active High 13 1 read-write TIASWCON TIA SW[11:0] Control 0 12 read-write LOWNOISE Work mode, vzero-vbias=0. 108 CAPA_LP CAPA test with LP TIA 20 NORM Normal work mode 44 DIO Normal work mode with back-back diode enabled. 45 SHORTSW Work mode with short switch protection 46 NSWFULLCON Switch Matrix Full Configuration (N) 0x154 32 read-write n 0x0 0x0 N1 Control of N1 Switch. Set Will Close N1, Unset Open 0 1 read-write N2 Control of N2 Switch. Set Will Close N2, Unset Open 1 1 read-write N3 Control of N3 Switch. Set Will Close N3, Unset Open 2 1 read-write N4 Control of N4 Switch. Set Will Close N4, Unset Open 3 1 read-write N5 Control of N5 Switch. Set Will Close N5, Unset Open 4 1 read-write N6 Control of N6 Switch. Set Will Close N6, Unset Open 5 1 read-write N7 Control of N7 Switch. Set Will Close N7, Unset Open 6 1 read-write N8 Control of N8 Switch. Set Will Close N8, Unset Open 7 1 read-write N9 Control of N9 Switch. Set Will Close N9, Unset Open 8 1 read-write Nl Control of NL Switch. 10 1 read-write NL2 Control of NL2 Switch. 11 1 read-write NR1 Control of Nr1 Switch. Set Will Close Nr1, Unset Open 9 1 read-write NSWSTA Switch Matrix Status (N) 0x1B8 32 read-write n 0x0 0x0 N1STA Status of N1 Switch. 0 1 read-only N2STA Status of N2 Switch. 1 1 read-only N3STA Status of N3 Switch. 2 1 read-only N4STA Status of N4 Switch. 3 1 read-only N5STA Status of N5 Switch. 4 1 read-only N6STA Status of N6 Switch. 5 1 read-only N7STA Status of N7 Switch. 6 1 read-only N8STA Status of N8 Switch. 7 1 read-only N9STA Status of N9 Switch. 8 1 read-only NL2STA Status of NL2 Switch. 11 1 read-only NLSTA Status of NL Switch. 10 1 read-only NR1STA Status of NR1 Switch. 9 1 read-only PMBW Power Mode Configuration 0x2F0 32 read-write n 0x0 0x0 SYSBW Configure System Bandwidth 2 2 read-write BWNA no action for system configuration 0 BW50 50kHz -3dB bandwidth 1 BW100 100kHz -3dB bandwidth 2 BW250 250kHz -3dB bandwidth 3 SYSHP Set High Speed DAC and ADC in High Power Mode 0 1 read-write LP LP mode 0 HP HP mode 1 PSWFULLCON Switch Matrix Full Configuration (P) 0x158 32 read-write n 0x0 0x0 P10 P10 Switch Control 9 1 read-write P11 Control of P11 Switch. Set Will Close P11, Unset Open 10 1 read-write P12 Control of P12 Switch. Set Will Close P12, Unset Open 11 1 read-write P2 Control of P2 Switch. Set Will Close P2, Unset Open 1 1 read-write P3 Control of P3 Switch. Set Will Close P3, Unset Open 2 1 read-write P4 Control of P4 Switch. Set Will Close P4, Unset Open 3 1 read-write P5 Control of P5 Switch. Set Will Close P5, Unset Open 4 1 read-write P6 Control of P6 Switch. Set Will Close P6, Unset Open 5 1 read-write P7 Control of P7 Switch. Set Will Close P7, Unset Open 6 1 read-write P8 Control of P8 Switch. Set Will Close P8, Unset Open 7 1 read-write P9 Control of P9 Switch. Set Will Close P9, Unset Open 8 1 read-write PL PL Switch Control 13 1 read-write PL2 PL2 Switch Control 14 1 read-write PR0 PR0 Switch Control 0 1 read-write PSWSTA Switch Matrix Status (P) 0x1B4 32 read-write n 0x0 0x0 P10STA Status of P10 Switch. 9 1 read-only P11STA Status of P11 Switch. 10 1 read-only P12STA Status of P12 Switch. 11 1 read-only P13STA Status of P13 Switch. 12 1 read-only P2STA Status of P2 Switch. 1 1 read-only P3STA Status of P3 Switch. 2 1 read-only P4STA Status of P4 Switch. 3 1 read-only P5STA Status of P5 Switch. 4 1 read-only P6STA Status of P6 Switch. 5 1 read-only P7STA Status of P7 Switch. 6 1 read-only P8STA Status of P8 Switch. 7 1 read-only P9STA Status of P9 Switch. 8 1 read-only PL2STA PL Switch Control 14 1 read-only PLSTA PL Switch Control 13 1 read-only PR0STA PR0 Switch Control 0 1 read-only REPEATADCCNV REPEAT ADC Conversions 0x1F0 32 read-write n 0x0 0x0 EN Enable Repeat ADC Conversions 0 1 read-write Dis Disable Repeat ADC Conversions 0 En Enable Repeat ADC Conversions 1 NUM Repeat Value 4 8 read-write SINC2DAT Supply Rejection Filter Result 0x80 32 read-write n 0x0 0x0 DATA LPF Result 0 16 read-write STATSCON Statistics Control 0x1C4 32 read-write n 0x0 0x0 RESRVED Reserved 1 3 read-write SAMPLENUM Sample Size 4 3 read-write STATSEN Statistics Enable 0 1 read-write DIS Disable Statistics 0 EN Enable Statistics 1 STDDEV Standard Deviation Configuration 7 5 read-write STATSMEAN Statistics Mean Output 0x1C8 32 read-write n 0x0 0x0 MEAN Mean Output 0 16 read-only STATSVAR Variance Output 0x1C0 32 read-write n 0x0 0x0 VARIANCE Statistical Variance Value 0 31 read-only SWCON Switch Matrix Configuration 0xC 32 read-write n 0x0 0x0 DMUXCON Control of D Switch MUX 0 4 read-write NMUXCON Control of N Switch MUX 8 4 read-write PMUXCON Control of P Switch MUX 4 4 read-write SWSOURCESEL Switch Control Select 16 1 read-write T10CON Control of T[10] 18 1 read-write T11CON Control of T[11] 19 1 read-write T9CON Control of T[9] 17 1 read-write TMUXCON Control of T Switch MUX. 12 4 read-write SWMUX Switch Mux for ECG 0x35C 32 read-write n 0x0 0x0 CMMUX CM Resistor Select for Ain2, Ain3 3 1 read-write SWMUX ECG Swmux Control 0 3 read-write TEMPCON0 Temp Sensor Configuration 0x174 32 read-write n 0x0 0x0 CHOPCON Temp Sensor Chop Mode 1 1 read-write DIS Disable chop 0 EN Enable chop 1 CHOPFRESEL Chop Mode Frequency Setting 2 2 read-write ENABLE Unused 0 1 read-write TEMPCON1 AFE_TEMPSEN_DIO 0x374 32 read-write n 0x0 0x0 EN Test Signal Enable 16 1 read-write On Turn On 0 Off Turn Off 1 ISWCON Bias Current Selection 0 16 read-write PWD Power Down Control 17 1 read-write Active Unknown 0 PowerDown Unknown 1 TEMPSENSDAT Temperature Sensor Result 0x84 32 read-write n 0x0 0x0 DATA Temp Sensor 0 16 read-write TESTDAC DAC Test 0x388 32 read-write n 0x0 0x0 LPFBYPEN Bypass Low Pass Filter Between Dac and Buffer 2 1 read-write TSWFULLCON Switch Matrix Full Configuration (T) 0x15C 32 read-write n 0x0 0x0 T1 Control of T1 Switch. Set Will Close T1, Unset Open 0 1 read-write T10 Control of T10 Switch. Set Will Close T10, Unset Open 9 1 read-write T11 Control of T11 Switch. Set Will Close T11, Unset Open 10 1 read-write T2 Control of T2 Switch. Set Will Close T2, Unset Open 1 1 read-write T3 Control of T3 Switch. Set Will Close T3, Unset Open 2 1 read-write T4 Control of T4 Switch. Set Will Close T4, Unset Open 3 1 read-write T5 Control of T5 Switch. Set Will Close T5, Unset Open 4 1 read-write T7 Control of T7 Switch. Set Will Close T7, Unset Open 6 1 read-write T9 Control of T9 Switch. Set Will Close T9, Unset Open 8 1 read-write TR1 Control of Tr1 Switch. Set Will Close Tr1, Unset Open 11 1 read-write TSWSTA Switch Matrix Status (T) 0x1BC 32 read-write n 0x0 0x0 T10STA Status of T10 Switch. 9 1 read-only T11STA Status of T11 Switch. 10 1 read-only T1STA Status of T1 Switch. 0 1 read-only T2STA Status of T2 Switch. 1 1 read-only T3STA Status of T3 Switch. 2 1 read-only T4STA Status of T4 Switch. 3 1 read-only T5STA Status of T5 Switch. 4 1 read-only T6STA Status of T6 Switch. 5 1 read-only T7STA Status of T7 Switch. 6 1 read-only T8STA Status of T8 Switch. 7 1 read-only T9STA Status of T9 Switch. 8 1 read-only TR1STA Status of TR1 Switch. 11 1 read-only WGAMPLITUDE Waveform Generator - Sinusoid Amplitude 0x3C 32 read-write n 0x0 0x0 SINEAMPLITUDE Sinusoid Amplitude 0 11 read-write WGCON Waveform Generator Configuration 0x14 32 read-write n 0x0 0x0 DACGAINCAL Bypass DAC Gain 5 1 read-write DACOFFSETCAL Bypass DAC Offset 4 1 read-write TYPESEL Selects the Type of Waveform 1 2 read-write WGFCW Waveform Generator - Sinusoid Frequency Control Word 0x30 32 read-write n 0x0 0x0 SINEFCW Sinusoid Generator Frequency Control Word 0 24 read-write WGOFFSET Waveform Generator - Sinusoid Offset 0x38 32 read-write n 0x0 0x0 SINEOFFSET Sinusoid Offset 0 12 read-write WGPHASE Waveform Generator - Sinusoid Phase Offset 0x34 32 read-write n 0x0 0x0 SINEOFFSET Sinusoid Phase Offset 0 20 read-write AFECON Unknown AFECON 0x0 0x0 0x100 registers n ADIID ADI Identification 0x0 16 read-write n 0x0 0x0 ADIID ADI Identifier. 0 16 read-only CHIPID Chip Identification 0x4 16 read-write n 0x0 0x0 PartID Part Identifier 4 12 read-only Revision Silicon Revision Number 0 4 read-only CLKCON0 Clock Divider Configuration 0x8 16 read-write n 0x0 0x0 ADCCLKDIV ADC Clock Divider Configuration 6 4 read-write SFFTCLKDIVCNT SFFT Clock Divider Configuration 10 6 read-write SYSCLKDIV System Clock Divider Configuration 0 6 read-write CLKCON0KEY Enable Clock Division to 8Mhz,4Mhz and 2Mhz 0x20 16 read-write n 0x0 0x0 divsysclk_ulp_en Enable Clock Division to 8Mhz,4Mhz and 2Mhz 0 16 read-write CLKEN1 Clock Gate Enable 0x10 16 read-write n 0x0 0x0 ACLKDIS ACLK Clock Enable 5 1 read-write GPT0DIS GPT0 Clock Enable 6 1 read-write GPT1DIS GPT1 Clock Enable 7 1 read-write CLKSEL Clock Select 0x14 16 read-write n 0x0 0x0 ADCCLKSEL Select ADC Clock Source 2 2 read-write SYSCLKSEL Select System Clock Source 0 2 read-write DIE2DIESTA DIE2DIESTA 0x28 16 read-write n 0x0 0x0 STA DIE2DIE Deadlock and Transaction Error Status 0 16 read-write DSPUPDATEEN DSP Update Enable 0x38 16 read-write n 0x0 0x0 DSPLOOP ADC Digital Logic Test 0 1 read-write GPIOCLKMUXSEL GPIO Clock MUX Select 0x1C 16 read-write n 0x0 0x0 SEL Configure Clock MUX Out to GPIO 0 3 read-write MKEY MKEY 0x34 16 read-write n 0x0 0x0 KEY Key to Unlock SWRSTCON 0 16 write-only AFECRC CRC Accelerator AFECRC 0x0 0x0 0x100 registers n CRCINTEN CRC Error Interrupt Enable Bit 0x24 32 read-write n 0x0 0x0 CRC_ERR_EN CRC Error Interrupt Enable Bit 0 1 read-write reserved_31_1 Reserved 1 31 read-write CRC_SIG_COMP CRC Signature Compare Data Input. 0x20 32 read-write n 0x0 0x0 CRC_SIG CRC Signature Compare Data Input. 0 32 read-write CTL CRC Control Register 0x0 32 read-write n 0x0 0x0 BITMIRR Bit Mirroring. 2 1 read-write BYTMIRR Byte Mirroring. 3 1 read-write EN CRC Peripheral Enable 0 1 read-write LSBFIRST LSB First Calculation Order 1 1 read-write MON_EN Enable Apb32/Apb16 to Get Address/Data for CRC Calculation 9 1 read-write RevID Revision ID 28 4 read-only W16SWP Word16 Swap Enabled. 4 1 read-write INTSTA CRC Error Interrupt Status Bit 0x28 32 read-write n 0x0 0x0 CRC_ERR_ST CRC Error Interrupt Status Bit 0 1 read-write IPBITS Input Data Bits 0x10 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBYTE Input Data Byte 0x14 8 read-write n 0x0 0x0 DATA_BYTE Input Data Byte. 0 8 write-only IPDATA Data Input. 0x4 32 read-write n 0x0 0x0 VALUE Data Input. 0 32 write-only POLY CRC Reduction Polynomial 0xC 32 read-write n 0x0 0x0 VALUE CRC Reduction Polynomial 0 32 read-write RESULT CRC Residue 0x8 32 read-write n 0x0 0x0 VALUE CRC Residue 0 32 read-write AFEWDT Unknown AFEWDT 0x0 0x0 0x100 registers n WDTCLRI Refresh Watchdog Register 0xC 16 read-write n 0x0 0x0 CLRWDG Refresh Register 0 16 write-only WDTCON Watchdog Timer Control Register 0x8 16 read-write n 0x0 0x0 CLKDIV2 Clock Source 8 1 read-write EN Timer Enable 5 1 read-write IRQ WDT Interrupt Enable 1 1 read-write Reset Watchdog Timer timeout creates a reset. 0 Interrupt Watchdog Timer timeout creates an interrupt instead of reset. 1 MDE Timer Mode Select 6 1 read-write MINLOAD_EN Timer Window Control 9 1 read-write PDSTOP Power Down Stop Enable 0 1 read-write Continue Continue Counting When In Hibernate 0 Stop Stop Counter When In Hibernate. 1 PRE Prescaler. 2 2 read-write Reserved1_7 Reserved 7 1 read-only RESERVED_15_11 RESERVED 11 5 read-write WDTIRQEN WDT Interrupt Enable 10 1 read-write WDTLD Watchdog Timer Load Value 0x0 16 read-write n 0x0 0x0 LOAD WDT Load Value 0 16 read-write WDTMINLD Minimum Load Value 0x1C 16 read-write n 0x0 0x0 MIN_LOAD WDT Min Load Value 0 16 read-write WDTSTA Timer Status 0x18 16 read-write n 0x0 0x0 CLRI WDTCLRI Write Status 1 1 read-only CON WDTCON Write Status 3 1 read-only IRQ WDT Interrupt 0 1 read-only Cleared Watchdog Timer Interrupt Not Pending 0 Pending Watchdog Timer Interrupt Pending 1 LOCK Lock Status 4 1 read-only Open Timer Operation Not Locked 0 Locked Timer Enabled and Locked 1 OTPWRDONE Reset Type Status 5 1 read-only RESERVED_15_7 RESERVED 7 9 read-write TLD WDTVAL Write Status 2 1 read-only Sync_Complete Arm and AFE Watchdog Clock Domains WDTLD values match 0 Sync_In_Progress Synchronize In Progress 1 TMINLD WDTMINLD Write Status 6 1 read-only WDTVALS Current Count Value 0x4 16 read-write n 0x0 0x0 CCOUNT Current WDT Count Value. 0 16 read-only AGPIO2 Unknown AGPIO2 0x0 0x0 0x40 registers n CLR GPIO Port Data Out Clear 0x1C 16 read-write n 0x0 0x0 CLR Set the output low for the port pin 0 16 write-only CON GPIO Port Configuration 0x0 32 read-write n 0x0 0x0 PIN0CFG Pin 0 Configuration Bits 0 2 read-write PIN1CFG Pin 1 Configuration Bits 2 2 read-write PIN2CFG Pin 2 Configuration Bits 4 2 read-write PIN3CFG Pin 3 Configuration Bits 6 2 read-write PIN4CFG Pin 4 Configuration Bits 8 2 read-write PIN5CFG Pin 5 Configuration Bits 10 2 read-write PIN6CFG Pin 6 Configuration Bits 12 2 read-write PIN7CFG Pin 7 Configuration Bits 14 2 read-write IEN GPIO Port Input Path Enable 0xC 16 read-write n 0x0 0x0 IEN Input path enable 0 16 read-write IN GPIO Port Registered Data Input 0x10 16 read-write n 0x0 0x0 IN Registered data input 0 16 read-only OEN GPIO Port Output Enable 0x4 16 read-write n 0x0 0x0 OEN Pin Output Drive enable 0 16 read-write OUT GPIO Port Data Output 0x14 16 read-write n 0x0 0x0 OUT Data out 0 16 read-write PE GPIO Port Pullup/Pulldown Enable 0x8 16 read-write n 0x0 0x0 PE Pin Pull enable 0 16 read-write SET GPIO Port Data Out Set 0x18 16 read-write n 0x0 0x0 SET Set the output HIGH for the pin 0 16 write-only TGL GPIO Port Pin Toggle 0x20 16 read-write n 0x0 0x0 TGL Toggle the output of the port pin 0 16 write-only AGPT0 General Purpose Timer AGPT0 0x0 0x0 0x40 registers n AGPT0_EVT AGPT0_EVT 64 ALD0 16-Bit Load Value, Asynchronous. 0x14 16 read-write n 0x0 0x0 ALOAD Load Value, Asynchronous 0 16 read-write AVAL0 16-Bit Timer Value, Asynchronous Register. 0x18 16 read-write n 0x0 0x0 AVAL Counter Value 0 16 read-only CAP0 Capture Register. 0x10 16 read-write n 0x0 0x0 CAP 16-bit Captured Value 0 16 read-only CLRI0 Clear Interrupt Register. 0xC 16 read-write n 0x0 0x0 CAP Clear Captured Event Interrupt 1 1 write-only TMOUT Clear Timeout Interrupt 0 1 write-only CON0 Control Register. 0x8 16 read-write n 0x0 0x0 CLK Clock Select 5 2 read-write ENABLE Timer Enable 4 1 read-write EVENT Event Select Range 8 5 read-write EVTEN Event Select 13 1 read-write MOD Timer Mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload Control 7 1 read-write RSTEN Counter and Prescale Reset Enable 14 1 read-write SYNCBYP Synchronization Bypass 15 1 read-write UP Count up 2 1 read-write INTEN Interrupt Enable 0x28 16 read-write n 0x0 0x0 INTEN Interrupt Enable 0 1 read-write LD0 16-bit Load Value Register. 0x0 16 read-write n 0x0 0x0 LOAD Load Value 0 16 read-write PWMCON0 PWM Control Register. 0x20 16 read-write n 0x0 0x0 IDLE PWM Idle State 1 1 read-write MATCHEN PWM Match Enabled 0 1 read-write PWMMAT0 PWM Match Value Register. 0x24 16 read-write n 0x0 0x0 MATCHVAL PWM Match Value 0 16 read-write STA0 Status Register. 0x1C 16 read-write n 0x0 0x0 BUSY Timer Busy 6 1 read-only CAP Capture Event Pending 1 1 read-only PDOK Clear Interrupt Register Synchronization 7 1 read-only RSTCNT Counter Reset Occurring 8 1 read-only TMOUT Timeout Event Occurred 0 1 read-only VAL0 16-Bit Timer Value Register. 0x4 16 read-write n 0x0 0x0 VAL Current Count 0 16 read-only AGPT1 General Purpose Timer AGPT1 0x0 0x0 0x40 registers n AGPT1_EVT AGPT1_EVT 65 ALD1 16-bit Load Value, Asynchronous Register 0x14 16 read-write n 0x0 0x0 ALOAD Load Value, Asynchronous 0 16 read-write AVAL1 16-bit Timer Value, Asynchronous Register 0x18 16 read-write n 0x0 0x0 AVAL Counter Value 0 16 read-only CAP1 Capture Register 0x10 16 read-write n 0x0 0x0 CAP 16-bit Captured Value. 0 16 read-only CLRI1 Clear Interrupt Register 0xC 16 read-write n 0x0 0x0 CAP Clear Captured Event Interrupt 1 1 write-only TMOUT Clear Timeout Interrupt 0 1 write-only CON1 Control Register 0x8 16 read-write n 0x0 0x0 CLK Clock Select 5 2 read-write ENABLE Timer Enable 4 1 read-write EVENT Event Select Range 8 5 read-write EVENTEN Event Select 13 1 read-write MOD Timer Mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload Control 7 1 read-write RSTEN Counter and Prescale Reset Enable 14 1 read-write SYNCBYP Synchronization Bypass 15 1 read-write UP Count up 2 1 read-write INTEN1 Interrupt Enable 0x28 16 read-write n 0x0 0x0 INTEN Interrupt Enable 0 1 read-write LD1 16-bit Load Value Register 0x0 16 read-write n 0x0 0x0 LOAD Load Value 0 16 read-write PWMCON1 PWM Control Register 0x20 16 read-write n 0x0 0x0 IDLE PWM Idle State. 1 1 read-write MATCHEN PWM Match Enabled. 0 1 read-write PWMMAT1 PWM Match Value Register 0x24 16 read-write n 0x0 0x0 MATCHVAL PWM Match Value 0 16 read-write STA1 Status Register 0x1C 16 read-write n 0x0 0x0 BUSY Timer Busy 6 1 read-only CAP Capture Event Pending 1 1 read-only PDOK Clear Interrupt Register Synchronization 7 1 read-only RSTCNT Counter Reset Occurring 8 1 read-only TMOUT Timeout Event Occurred 0 1 read-only VAL1 16-bit Timer Value Register 0x4 16 read-write n 0x0 0x0 VAL Current Count 0 16 read-only ALLON Always On Register ALLON 0x0 0x0 0x100 registers n CLKEN0 32KHz Peripheral Clock Enable 0x70 16 read-write n 0x0 0x0 SLPWUTDIS Sleep/Wakeup Timer Clock Disable 1 1 read-write TIACHPDIS TIA Chop Clock Disable 2 1 read-write WDTDIS Watch Dog Timer Clock Disable 0 1 read-write EI2CON External Interrupt Configuration 2 0x28 16 read-write n 0x0 0x0 BUSINTEN BUS Interrupt Detection Enable Bit 3 1 read-write BUSINTMDE BUS Interrupt Detection Mode Registers 0 3 read-write EICLR External Interrupt Clear 0x30 16 read-write n 0x0 0x0 AUTCLRBUSEN Enable Auto Clear of Bus Interrupt 15 1 read-write BUSINT BUS Interrupt 8 1 read-write OSCCON Oscillator Control 0x10 16 read-write n 0x0 0x0 HFOSCEN High Frequency Internal Oscillator Enable 1 1 read-write HFOSCOK Status of HFOSC Oscillator 9 1 read-only HFXTALEN High Frequency Crystal Oscillator Enable 2 1 read-write HFXTALOK Status of HFXTAL Oscillator 10 1 read-only LFOSCEN Low Frequency Internal Oscillator Enable 0 1 read-write LFOSCOK Status of LFOSC Oscillator 8 1 read-only OSCKEY Key Protection for OSCCON 0xC 16 read-write n 0x0 0x0 OSCKEY Oscillator Control Key Register. 0 16 read-write PMUSTA PMU Status 0x44 16 read-write n 0x0 0x0 PMUSTATE PMU FSM States 0 3 read-only PWRKEY Key Protection for PWRMOD 0x4 16 read-write n 0x0 0x0 PWRKEY PWRMOD Key Register 0 16 read-write PWRMOD Power Modes 0x0 16 read-write n 0x0 0x0 PWRMOD Power Mode Control Bits 0 2 read-write RSTSTA Reset Status 0x40 16 read-write n 0x0 0x0 EXTRST External Reset 1 1 read-write MMRSWRST MMR Software Reset 3 1 read-write POR Power-on Reset 0 1 read-write WDRST Watchdog Timeout 2 1 read-write BUSM0 Bus matrix BUSM0 0x0 0x0 0x50 registers n ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 0x0 32 read-write n 0x0 0x0 FLSH_DCODE Flash priority for DCODE 0 2 read-write FLSH_DMA0 Flash priority for DMA0 4 2 read-write FLSH_SBUS Flash priority for SBUS 2 2 read-write SRAM0_DCODE SRAM0 priority for Dcode 16 2 read-write SRAM0_DMA0 SRAM0 priority for DMA0 20 2 read-write SRAM0_SBUS SRAM0 priority for SBUS 18 2 read-write ARBIT1 Arbitration Priority Configuration for SRAM1 and SIP 0x4 32 read-write n 0x0 0x0 SIP_DCODE SIP priority for DCODE 16 2 read-write SIP_DMA0 SIP priority for DMA0 20 2 read-write SIP_SBUS SIP priority for SBUS 18 2 read-write SRAM1_DCODE SRAM1 priority for Dcode 0 2 read-write SRAM1_DMA0 SRAM1 priority for DMA0 4 2 read-write SRAM1_SBUS SRAM1 priority for SBUS 2 2 read-write ARBIT2 Arbitration Priority Configuration for APB32 and APB16 0x8 32 read-write n 0x0 0x0 APB16_DCODE APB16 priority for DCODE 16 2 read-write APB16_DMA0 APB16 priority for DMA0 20 2 read-write APB16_SBUS APB16 priority for SBUS 18 2 read-write APB32_DCODE APB32 priority for DCODE 0 2 read-write APB32_DMA0 APB32 priority for DMA0 4 2 read-write APB32_SBUS APB32 priority for SBUS 2 2 read-write ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 0xC 32 read-write n 0x0 0x0 APB16_4DMA_CORE APB16 for dma priority for CORE 16 1 read-write APB16_4DMA_DMA1 APB16 for dma priority for DMA1 17 1 read-write APB16_CORE APB16 priority for CORE 0 1 read-write APB16_DMA1 APB16 priority for DMA1 1 1 read-write CLKG0_CLK Clocking CLKG0_CLK 0x0 0x0 0x50 registers n CTL0 Misc clock settings 0x0 32 read-write n 0x0 0x0 CLKMUX Clock mux select 0 2 read-write HFXTALIE High frequency crystal interrupt enable 15 1 read-write LFXTALIE Low frequency crystal interrupt enable 14 1 read-write RCLKMUX Flash reference clock and HPBUCK clock source mux 8 2 read-write SPLLIPSEL SPLL source select mux 11 1 read-write CTL1 Clock dividers 0x4 32 read-write n 0x0 0x0 ACLKDIVCNT ACLK Divide Count. 16 8 read-write HCLKDIVCNT HCLK divide count 0 6 read-write PCLKDIVCNT PCLK divide count 8 6 read-write CTL3 System PLL 0xC 32 read-write n 0x0 0x0 SPLLDIV2 System PLL division by 2 8 1 read-write SPLLEN System PLL enable 9 1 read-write SPLLIE System PLL interrupt enable 10 1 read-write SPLLMSEL System PLL M Divider 11 4 read-write SPLLMUL2 system PLL multiply by 2 16 1 read-write SPLLNSEL System PLL N multiplier 0 5 read-write CTL5 User clock gating control 0x14 32 read-write n 0x0 0x0 GPIOCLKOFF GPIO clock control 4 1 read-write GPTCLK0OFF GP timer 0 user control 0 1 read-write GPTCLK1OFF GP timer 1 user control 1 1 read-write GPTCLK2OFF GP timer 2 user control 2 1 read-write PERCLKOFF This bit is used to disable all clocks connected to all peripherals 5 1 read-write UCLKI2COFF I2C clock user control 3 1 read-write STAT0 Clocking status 0x18 32 read-write n 0x0 0x0 HFXTAL HF crystal status 12 1 read-only HFXTALNOK HF crystal not stable 14 1 read-write HFXTALOK HF crystal stable 13 1 read-write LFXTAL LF crystal status 8 1 read-only LFXTALNOK LF crystal not stable 10 1 read-write LFXTALOK LF crystal stable 9 1 read-write SPLL System PLL status 0 1 read-only SPLLLK System PLL lock 1 1 read-write SPLLUNLK System PLL unlock 2 1 read-write CLKG0_OSC Clocking CLKG0_OSC 0x0 0x0 0x50 registers n CTL Oscillator Control 0x10 32 read-write n 0x0 0x0 HFOSCEN High frequency internal oscillator enable 1 1 read-write HFOSCOK Status of HFOSC oscillator 9 1 read-only HFXTALEN High frequency crystal oscillator enable 3 1 read-write HFXTALOK Status of HFXTAL oscillator 11 1 read-only LFCLKMUX 32 KHz clock select mux 0 1 read-write LFOSCOK Status of LFOSC oscillator 8 1 read-only LFXTALEN Low frequency crystal oscillator enable 2 1 read-write LFXTALOK Status of LFXTAL oscillator 10 1 read-only LFXTAL_BYPASS Low frequency crystal oscillator Bypass 4 1 read-write LFXTAL_MON_EN LFXTAL clock monitor and Clock FAIL interrupt enable 5 1 read-write LFXTAL_MON_FAIL_STAT LF XTAL (crystal clock) Not Stable 31 1 read-write KEY Key Protection for OSCCTRL 0xC 32 read-write n 0x0 0x0 VALUE Oscillator key 0 16 write-only CRC0 CRC Accelerator CRC0 0x0 0x0 0x100 registers n CTL CRC Control Register 0x0 32 read-write n 0x0 0x0 BITMIRR Bit Mirroring 2 1 read-write BYTMIRR Byte Mirroring 3 1 read-write EN CRC Peripheral Enable 0 1 read-write LSBFIRST LSB First Calculation Order 1 1 read-write RevID Revision ID 28 4 read-only W16SWP Word16 Swap 4 1 read-write IPBITS0 Input Data Bits 0x10 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS1 Input Data Bits 0x11 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS2 Input Data Bits 0x12 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS3 Input Data Bits 0x13 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS4 Input Data Bits 0x14 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS5 Input Data Bits 0x15 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS6 Input Data Bits 0x16 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS7 Input Data Bits 0x17 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[0] Input Data Bits 0x20 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[1] Input Data Bits 0x31 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[2] Input Data Bits 0x43 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[3] Input Data Bits 0x56 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[4] Input Data Bits 0x6A 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[5] Input Data Bits 0x7F 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[6] Input Data Bits 0x95 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBITS[7] Input Data Bits 0xAC 8 read-write n 0x0 0x0 DATA_BITS Input Data Bits. 0 8 write-only IPBYTE Input Data Byte IPBITS0 0x10 8 read-write n 0x0 0x0 DATA_BYTE Input Data Byte. 0 8 write-only IPDATA Input Data Word Register 0x4 32 read-write n 0x0 0x0 VALUE Data Input. 0 32 write-only POLY Programmable CRC Polynomial 0xC 32 read-write n 0x0 0x0 VALUE CRC Reduction Polynomial 0 32 read-write RESULT CRC Result Register 0x8 32 read-write n 0x0 0x0 VALUE CRC Residue 0 32 read-write CRYPT0 Cryptogaphic CRYPT0 0x0 0x0 0x2C registers n CRYPT_EVT Event 38 AESKEY0 Key Bits[ 31:0 ] 0x2C 32 read-write n 0x0 0x0 VALUE Key: Bytes [3:0] 0 32 write-only AESKEY1 Key Bits [ 63:32 ] 0x30 32 read-write n 0x0 0x0 VALUE Key: Bytes [7:4] 0 32 write-only AESKEY2 Key Bits [ 95:64 ] 0x34 32 read-write n 0x0 0x0 VALUE Key: Bytes [11:8] 0 32 write-only AESKEY3 Key Bits [ 127:96 ] 0x38 32 read-write n 0x0 0x0 VALUE Key: Bytes [15:12] 0 32 write-only AESKEY4 Key Bits [ 159:128 ] 0x3C 32 read-write n 0x0 0x0 VALUE Key: Bytes [3:0] 0 32 write-only AESKEY5 Key Bits [ 191:160 ] 0x40 32 read-write n 0x0 0x0 VALUE Key: Bytes [7:4] 0 32 write-only AESKEY6 Key Bits [ 223:192 ] 0x44 32 read-write n 0x0 0x0 VALUE Key: Bytes [11:8] 0 32 write-only AESKEY7 Key Bits [ 255:224 ] 0x48 32 read-write n 0x0 0x0 VALUE Key: Bytes [15:12] 0 32 write-only CCM_NUM_VALID_BYTES NUM_VALID_BYTES 0x74 32 read-write n 0x0 0x0 NUM_VALID_BYTES Number of Valid Bytes in CCM Last Data 0 4 read-write RESERVED_31_4 Reserved 4 28 read-write CFG Configuration Register 0x0 32 read-write n 0x0 0x0 BLKEN Enable BIT for the Crypto Block 0 1 read-write Enable Enable Crypto Block 0 Disable Disable Crypto Block 1 CBCEN Enable CBC Mode Operation 18 1 read-write CCMEN Enable CCM/CCM* Mode Operation 19 1 read-write CMACEN Enable CMAC Mode Operation 20 1 read-write CTREN Enable CTR Mode Operation 17 1 read-write ECBEN Enable ECB Mode Operation 16 1 read-write ENCR Encrypt or Decrypt 1 1 read-write ENDIAN Endianness 6 1 read-write Little_Endian Little Endian Format 0 Big_Endian Big Endian Format 1 INDMAEN Enable DMA for Input Buffer 2 1 read-write DMA_DISABLE_INBUF Disable DMA Requesting for Input Buffer 0 DMA_ENABLE_INBUF Enable DMA Requesting for Input Buffer 1 INFLUSH Input Buffer Flush 4 1 write-only KEYLEN Select Key Length for AES Cipher 8 2 read-write OUTDMAEN Enable DMA for Output Buffer 3 1 read-write DMA_DISABLE_OUTBUF Disable DMA Requesting for Output Buffer 0 DMA_ENABLE_OUTBUF Enable DMA Requesting for Output Buffer 1 OUTFLUSH Output Buffer Flush 5 1 write-only RevID Rev ID for Crypto on Glue Micro 28 4 read-write SHA256EN Enable SHA-256 Operation 25 1 read-write SHADATSRC Select Data Input Source to SHA Engine 27 1 read-write INBUF SHA takes input from input buffer 0 OPBUF SHA takes input from output buffer 1 SHAINIT Restarts SHA Computation 26 1 read-write CNTRINIT Counter Initialization Vector 0x4C 32 read-write n 0x0 0x0 VALUE Counter Initialization Value 0 20 read-write DATALEN Payload Data Length 0x4 32 read-write n 0x0 0x0 VALUE Length of Payload Data 0 20 read-write INBUF Input Buffer 0x14 32 read-write n 0x0 0x0 VALUE Input Buffer 0 32 write-only INTEN Interrupt Enable Register 0xC 32 read-write n 0x0 0x0 INOVREN Enable Input Overflow Interrupt. 2 1 read-write INRDYEN Enable Input Ready Interrupt 0 1 read-write OUTRDYEN Enables the Output Ready Interrupt. 1 1 read-write OUTUNDREN Enable the Output Underflow Interrupt 3 1 read-write SHADONEN Enable SHA_Done Interrupt 5 1 read-write NONCE0 Nonce Bits [31:0] 0x1C 32 read-write n 0x0 0x0 VALUE Word 0: Nonce : Bits [31:0] 0 32 read-write NONCE1 Nonce Bits [63:32] 0x20 32 read-write n 0x0 0x0 VALUE Word 1: Nonce : Bits [63:32] 0 32 read-write NONCE2 Nonce Bits [95:64] 0x24 32 read-write n 0x0 0x0 VALUE Word 2: Nonce : Bits [95:64] 0 32 read-write NONCE3 Nonce Bits [127:96] 0x28 32 read-write n 0x0 0x0 VALUE Word 3: Nonce : Bits [127:96] 0 32 read-write OUTBUF Output Buffer 0x18 32 read-write n 0x0 0x0 VALUE Output Buffer 0 32 read-only PREFIXLEN Authentication Data Length 0x8 32 read-write n 0x0 0x0 VALUE Length of Associated Data 0 16 read-write SHAH0 SHA Bits [ 31:0 ] 0x50 32 read-write n 0x0 0x0 SHAHASH0 Word 0: SHA Hash 0 32 read-write SHAH1 SHA Bits [ 63:32 ] 0x54 32 read-write n 0x0 0x0 SHAHASH1 Word 1: SHA Hash 0 32 read-write SHAH2 SHA Bits [ 95:64 ] 0x58 32 read-write n 0x0 0x0 SHAHASH2 Word 2: SHA Hash 0 32 read-write SHAH3 SHA Bits [ 127:96 ] 0x5C 32 read-write n 0x0 0x0 SHAHASH3 Word 3: SHA Hash 0 32 read-write SHAH4 SHA Bits [ 159:128 ] 0x60 32 read-write n 0x0 0x0 SHAHASH4 Word 4: SHA Hash 0 32 read-write SHAH5 SHA Bits [ 191:160 ] 0x64 32 read-write n 0x0 0x0 SHAHASH5 Word 5: SHA Hash 0 32 read-write SHAH6 SHA Bits [ 223:192] 0x68 32 read-write n 0x0 0x0 SHAHASH6 Word 6: SHA Hash 0 32 read-write SHAH7 SHA Bits [ 255:224 ] 0x6C 32 read-write n 0x0 0x0 SHAHASH7 Word 7: SHA Hash 0 32 read-write SHA_LAST_WORD SHA Last Word and Valid Bits Information 0x70 32 read-write n 0x0 0x0 O_Bits_Valid Bits Valid in SHA Last Word Input 1 5 read-write O_Last_Word Last SHA Input Word 0 1 read-write STAT Status Register 0x10 32 read-write n 0x0 0x0 INOVR Overflow in the INPUT Buffer. 2 1 read-write INRDY Input Buffer Status 0 1 read-only INWORDS Number of Words in the Input Buffer 7 3 read-only OUTRDY Output Data Ready 1 1 read-only OUTUNDR Underflow Interrupt in the Output 3 1 read-write OUTWORDS Number of Words in the Output Buffer 10 3 read-only SHABUSY SHA Busy. in Computation 6 1 read-only SHADONE SHA Computation Complete 5 1 read-only DMA0 DMA DMA0 0x0 0x0 0x1000 registers n DMA_CHAN_ERR DMA Error 19 DMA0_CH0_DONE Channel SPI1_TX Done 20 DMA0_CH1_DONE Channel SPI1_RX Done 21 DMA0_CH2_DONE Channel 2 Done 22 DMA0_CH3_DONE Channel 3 Done 23 DMA0_CH4_DONE Channel SPI0_TX Done 24 DMA0_CH5_DONE Channel SPI0_RX Done 25 DMA0_CH6_DONE Channel 6 Done 26 DMA0_CH7_DONE Channel 7 Done 27 DMA0_CH8_DONE Channel UART_TX Done 28 DMA0_CH9_DONE Channel UART_RX Done 29 DMA0_CH10_DONE Channel I2C0_STX Done 30 DMA0_CH11_DONE Channel I2C0_SRX Done 31 DMA0_CH12_DONE Channel I2C0_MX Done 32 DMA0_CH13_DONE Channel AES_IN_Done 33 DMA0_CH14_DONE Channel AES_OUT_Done 34 DMA0_CH15_DONE Channel FLASH0_Done 35 DMA0_CH16_DONE AFE_DMA_CMDFIFO 56 DMA0_CH17_DONE AFE_DMA_DATAFIFO 57 DMA0_CH18_DONE Channel 18 Done 58 DMA0_CH19_DONE Channel 19 Done 59 DMA0_CH20_DONE Channel 20 Done 60 DMA0_CH21_DONE Channel 21 Done 61 DMA0_CH22_DONE Channel 22 Done 62 DMA0_CH23_DONE Channel 23 Done 63 ADBPTR DMA channel alternate control data base pointer 0xC 32 read-write n 0x0 0x0 ADDR Base address of the alternate data structure 0 32 read-only ALT_CLR DMA channel primary-alternate clear 0x34 32 read-write n 0x0 0x0 CHAN Select primary data struct 0 24 write-only ALT_SET DMA channel primary-alternate set 0x30 32 read-write n 0x0 0x0 CHAN Control struct status / select alt struct 0 24 read-write BS_CLR DMA channel bytes swap enable clear 0x804 32 read-write n 0x0 0x0 CHAN Disable byte swap 0 24 write-only BS_SET DMA channel bytes swap enable set 0x800 32 read-write n 0x0 0x0 CHAN Byte swap status 0 24 read-write CFG DMA Configuration 0x4 32 read-write n 0x0 0x0 MEN Controller enable 0 1 write-only DSTADDR_CLR DMA channel destination address decrement enable clear 0x81C 32 read-write n 0x0 0x0 CHAN Disable destination address decrement 0 24 write-only DSTADDR_SET DMA channel destination address decrement enable set 0x818 32 read-write n 0x0 0x0 CHAN Destination Address decrement status / configure destination address decrement 0 24 read-write EN_CLR DMA channel enable clear 0x2C 32 read-write n 0x0 0x0 CHAN Disable DMA channels 0 24 write-only EN_SET DMA channel enable set 0x28 32 read-write n 0x0 0x0 CHAN Enable DMA channels 0 24 read-write ERRCHNL_CLR DMA Per Channel Error Clear 0x48 32 read-write n 0x0 0x0 CHAN Per channel Bus error status/ Per channel bus error clear 0 24 read-write ERR_CLR DMA bus error clear 0x4C 32 read-write n 0x0 0x0 CHAN Bus error status 0 24 read-write INVALIDDESC_CLR DMA Per Channel Invalid Descriptor Clear 0x50 32 read-write n 0x0 0x0 CHAN Per channel Invalid Descriptor status/ Per channel Invalid descriptor status clear 0 24 read-write PDBPTR DMA channel primary control data base pointer 0x8 32 read-write n 0x0 0x0 ADDR Pointer to the base address of the primary data structure 0 32 read-write PRI_CLR DMA channel priority clear 0x3C 32 read-write n 0x0 0x0 CHPRICLR Configure channel for default priority level 0 24 write-only PRI_SET DMA channel priority set 0x38 32 read-write n 0x0 0x0 CHAN Configure channel for high priority 0 24 write-only REVID DMA Controller Revision ID 0xFE0 32 read-write n 0x0 0x0 VALUE DMA Controller revision ID 0 8 read-only RMSK_CLR DMA channel request mask clear 0x24 32 read-write n 0x0 0x0 CHAN Clear Request Mask Set bits 0 24 write-only RMSK_SET DMA channel request mask set 0x20 32 read-write n 0x0 0x0 CHAN Mask requests from DMA channels 0 24 read-write SRCADDR_CLR DMA channel source address decrement enable clear 0x814 32 read-write n 0x0 0x0 CHAN Disable source address decrement 0 24 write-only SRCADDR_SET DMA channel source address decrement enable set 0x810 32 read-write n 0x0 0x0 CHAN Source Address decrement status / configure Source address decrement 0 24 read-write STAT DMA Status 0x0 32 read-write n 0x0 0x0 CHANM1 Number of available DMA channels minus 1 16 5 read-only MEN Enable status of the controller 0 1 read-only SWREQ DMA channel software request 0x14 32 read-write n 0x0 0x0 CHAN Generate software request 0 24 write-only FLCC0 Flash Controller FLCC0 0x0 0x0 0x100 registers n ABORT_EN_HI IRQ Abort Enable (upper bits) 0x40 32 read-write n 0x0 0x0 VALUE VALUE[63:32] Sys IRQ abort enable 0 32 read-write ABORT_EN_LO IRQ Abort Enable (lower bits) 0x3C 32 read-write n 0x0 0x0 VALUE VALUE[31:0] Sys IRQ abort enable 0 32 read-write ADI_POR_SEC ADI flash security 0x50 32 read-write n 0x0 0x0 SECURE Set this bit to prevent read or write access to User Space (sticky when set) 0 1 read-write CMD Command 0x8 32 read-write n 0x0 0x0 VALUE Commands 0 4 read-write IDLE IDLE 0 ABORT ABORT 1 SLEEP Requests flash to enter Sleep mode 2 SIGN SIGN 3 WRITE WRITE 4 BLANK_CHECK Checks all of User Space fails if any bits in user space are cleared 5 ERASEPAGE ERASEPAGE 6 MASSERASE MASSERASE 7 ECC_ADDR ECC Status (Address) 0x48 32 read-write n 0x0 0x0 VALUE This register has the address for which ECC error is detected 0 19 read-only ECC_CFG ECC Config 0x44 32 read-write n 0x0 0x0 EN ECC Enable 0 1 read-write INFOEN Info space ECC Enable bit 1 1 read-write PTR ECC start page pointer (user should write bits [31:8] of the start page address into bits [31:8] of this register) 8 24 read-write IEN Interrupt Enable 0x4 32 read-write n 0x0 0x0 CMDCMPLT Command complete interrupt enable 0 1 read-write CMDFAIL Command fail interrupt enable 2 1 read-write ECC_CORRECT Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events 4 2 read-write NONE_cor Do not generate a response to ECC events 0 BUS_ERR_cor Generate Bus Errors in response to ECC events 1 IRQ_cor Generate IRQs in response to ECC events 2 ECC_ERROR Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events 6 2 read-write NONE_err Do not generate a response to ECC events 0 BUS_ERR_err Generate Bus Errors in response to ECC events 1 IRQ_err Generate IRQs in response to ECC events 2 WRALCMPLT Write almost complete interrupt enable 1 1 read-write KEY Key 0x20 32 read-write n 0x0 0x0 VALUE Key register 0 32 write-only KH_ADDR WRITE Address 0xC 32 read-write n 0x0 0x0 VALUE Address to be written on a WRITE command 3 16 read-write KH_DATA0 WRITE Lower Data 0x10 32 read-write n 0x0 0x0 VALUE Lower half of 64-bit dual word data to be written on a WRITE command 0 32 read-write KH_DATA1 WRITE Upper Data 0x14 32 read-write n 0x0 0x0 VALUE Upper half of 64-bit dual word data to be written on a WRITE command 0 32 read-write PAGE_ADDR0 Lower Page Address 0x18 32 read-write n 0x0 0x0 VALUE Lower address bits of the page address 10 9 read-write PAGE_ADDR1 Upper Page Address 0x1C 32 read-write n 0x0 0x0 VALUE Upper address bits of the page address 10 9 read-write SIGNATURE Signature 0x2C 32 read-write n 0x0 0x0 VALUE Provides read access to the most recently generated signature 0 32 read-only STAT Status 0x0 32 read-write n 0x0 0x0 CACHESRAMPERR SRAM parity errors in Cache Controller 29 1 read-only CMDBUSY Command busy 0 1 read-only CMDCOMP Command complete 2 1 read-only CMDFAIL Provides information on command failures 4 2 read-only ECCDCODE DCode AHB Bus Error ECC status 27 2 read-only ECCERRCMD ECC errors detected during user issued SIGN command 7 2 read-only ECCERRCNT ECC correction counter 17 3 read-only ECCICODE ICode AHB Bus Error ECC status 25 2 read-only ECCINFOSIGN ECC status of flash initialization 15 2 read-only ECCRDERR ECC IRQ cause 9 2 read-only INIT Flash controller initialization in progress 14 1 read-only OVERLAP Overlapping Command 11 1 read-write SIGNERR Signature check failure during initialization 13 1 read-only SLEEPING Flash array is in low power (sleep) mode 6 1 read-only WRALCOMP Write almost complete 3 1 read-only WRCLOSE WRITE registers are closed 1 1 read-only TIME_PARAM0 Time Parameter 0 0x34 32 read-write n 0x0 0x0 DIVREFCLK Divide Reference Clock (by 2) 0 1 read-write TERASE Erase Time 24 4 read-write TNVH NVSTR Hold time 16 4 read-write TNVH1 NVSTR Hold time during Mass Erase 28 4 read-write TNVS PROG/ERASE to NVSTR setup time 4 4 read-write TPGS NVSTR to Program setup time 8 4 read-write TPROG Program time 12 4 read-write TRCV Recovery time 20 4 read-write TIME_PARAM1 Time parameter 1 0x38 32 read-write n 0x0 0x0 TWK Wake up time 0 4 read-write UCFG User Configuration 0x30 32 read-write n 0x0 0x0 AUTOINCEN Auto address increment for Key hole access 1 1 read-write KHDMAEN Key Hole DMA enable 0 1 read-write WRPROT Write Protection 0x28 32 read-write n 0x0 0x0 WORD Clear bits to write protect related groups of user space pages. Once cleared these bits can only be set again by resetting the part 0 32 read-write WR_ABORT_ADDR Write Abort Address 0x24 32 read-write n 0x0 0x0 VALUE Holds the address targeted by an ongoing write command and retains its value after an ABORT event 0 32 read-only FLCC0_CACHE Cache Controller FLCC0_CACHE 0x0 0x0 0x100 registers n KEY Cache Key register 0x8 32 read-write n 0x0 0x0 VALUE Cache Key register 0 32 write-only SETUP Cache Setup register 0x4 32 read-write n 0x0 0x0 ICEN If this bit set, then I-Cache is enabled for AHB accesses. If 0, then I-cache is disabled, and all AHB accesses will be via Flash memory. 0 1 read-write STAT Cache Status register 0x0 32 read-write n 0x0 0x0 ICEN If this bit is set then I-Cache is enabled and when cleared I-Cache is disabled. 0 1 read-only GPIO0 Unknown GPIO0 0x0 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0x0 PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0x0 VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0x0 VALUE Drive strength select 0 16 read-write IEN Port Input Path Enable 0xC 16 read-write n 0x0 0x0 VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0x0 VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0x0 VALUE Interrupt B enable 0 16 read-write IN Port registered data input 0x10 16 read-write n 0x0 0x0 VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0x0 VALUE Interrupt Status 0 16 read-write OEN Port output enable 0x4 16 read-write n 0x0 0x0 VALUE Pin Output Drive enable 0 16 read-write OUT Port data output 0x14 16 read-write n 0x0 0x0 VALUE Data out 0 16 read-write PE Port output pullup/pulldown enable 0x8 16 read-write n 0x0 0x0 VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0x0 VALUE Interrupt polarity 0 16 read-write SET Port data out set 0x18 16 read-write n 0x0 0x0 VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0x0 VALUE Toggle the output of the port pin 0 16 write-only GPIO1 Unknown GPIO0 0x0 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0x0 PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0x0 VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0x0 VALUE Drive strength select 0 16 read-write IEN Port Input Path Enable 0xC 16 read-write n 0x0 0x0 VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0x0 VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0x0 VALUE Interrupt B enable 0 16 read-write IN Port registered data input 0x10 16 read-write n 0x0 0x0 VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0x0 VALUE Interrupt Status 0 16 read-write OEN Port output enable 0x4 16 read-write n 0x0 0x0 VALUE Pin Output Drive enable 0 16 read-write OUT Port data output 0x14 16 read-write n 0x0 0x0 VALUE Data out 0 16 read-write PE Port output pullup/pulldown enable 0x8 16 read-write n 0x0 0x0 VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0x0 VALUE Interrupt polarity 0 16 read-write SET Port data out set 0x18 16 read-write n 0x0 0x0 VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0x0 VALUE Toggle the output of the port pin 0 16 write-only GPIO2 Unknown GPIO0 0x0 0x0 0x50 registers n CFG Port Configuration 0x0 32 read-write n 0x0 0x0 PIN00 Pin 0 configuration bits 0 2 read-write PIN01 Pin 1 configuration bits 2 2 read-write PIN02 Pin 2 configuration bits 4 2 read-write PIN03 Pin 3 configuration bits 6 2 read-write PIN04 Pin 4 configuration bits 8 2 read-write PIN05 Pin 5 configuration bits 10 2 read-write PIN06 Pin 6 configuration bits 12 2 read-write PIN07 Pin 7 configuration bits 14 2 read-write PIN08 Pin 8 configuration bits 16 2 read-write PIN09 Pin 9 configuration bits 18 2 read-write PIN10 Pin 10 configuration bits 20 2 read-write PIN11 Pin 11 configuration bits 22 2 read-write PIN12 Pin 12 configuration bits 24 2 read-write PIN13 Pin 13 configuration bits 26 2 read-write PIN14 Pin 14 configuration bits 28 2 read-write PIN15 Pin 15 configuration bits 30 2 read-write CLR Port Data Out Clear 0x1C 16 read-write n 0x0 0x0 VALUE Set the output low for the port pin 0 16 write-only DS Port Drive Strength Select 0x34 16 read-write n 0x0 0x0 VALUE Drive strength select 0 16 read-write IEN Port Input Path Enable 0xC 16 read-write n 0x0 0x0 VALUE Input path enable 0 16 read-write IENA Port Interrupt A Enable 0x28 16 read-write n 0x0 0x0 VALUE Interrupt A enable 0 16 read-write IENB Port Interrupt B Enable 0x2C 16 read-write n 0x0 0x0 VALUE Interrupt B enable 0 16 read-write IN Port registered data input 0x10 16 read-write n 0x0 0x0 VALUE Registered data input 0 16 read-only INT Port Interrupt Status 0x30 16 read-write n 0x0 0x0 VALUE Interrupt Status 0 16 read-write OEN Port output enable 0x4 16 read-write n 0x0 0x0 VALUE Pin Output Drive enable 0 16 read-write OUT Port data output 0x14 16 read-write n 0x0 0x0 VALUE Data out 0 16 read-write PE Port output pullup/pulldown enable 0x8 16 read-write n 0x0 0x0 VALUE Pin Pull enable 0 16 read-write POL Port Interrupt Polarity 0x24 16 read-write n 0x0 0x0 VALUE Interrupt polarity 0 16 read-write SET Port data out set 0x18 16 read-write n 0x0 0x0 VALUE Set the output HIGH for the pin 0 16 write-only TGL Port Pin Toggle 0x20 16 read-write n 0x0 0x0 VALUE Toggle the output of the port pin 0 16 write-only I2C0 I2C Master/Slave I2C0 0x0 0x0 0x2C registers n I2C_SLV_EVT Slave Event 17 I2C_MST_EVT Master Event 18 ADDR1 1st master address byte 0x18 16 read-write n 0x0 0x0 VALUE Address byte 1 0 8 read-write ADDR2 2nd master address byte 0x1C 16 read-write n 0x0 0x0 VALUE Address byte 2 0 8 read-write ALT Hardware general call ID 0x38 16 read-write n 0x0 0x0 ID Slave Alt 0 8 read-write ASTRETCH_SCL Automatic stretch SCL register 0x58 16 read-write n 0x0 0x0 MST master automatic stretch mode 0 4 read-write MSTTMO master automatic stretch timeout 8 1 read-only SLV slave automatic stretch mode 4 4 read-write SLVTMO slave automatic stretch timeout 9 1 read-only BYT Start byte 0x20 16 read-write n 0x0 0x0 SBYTE Start byte 0 8 read-write DIV Serial clock period divisor 0x24 16 read-write n 0x0 0x0 HIGH Serial clock high time 8 8 read-write LOW Serial clock low time 0 8 read-write ID0 1st slave address device ID 0x3C 16 read-write n 0x0 0x0 VALUE Slave device ID 0 0 8 read-write ID1 2nd slave address device ID 0x40 16 read-write n 0x0 0x0 VALUE Slave device ID 1 0 8 read-write ID2 3rd slave address device ID 0x44 16 read-write n 0x0 0x0 VALUE Slave device ID 2 0 8 read-write ID3 4th slave address device ID 0x48 16 read-write n 0x0 0x0 VALUE Slave device ID 3 0 8 read-write MCRXCNT Master current receive data count 0x14 16 read-write n 0x0 0x0 VALUE Current receive count 0 8 read-only MCTL Master control 0x0 16 read-write n 0x0 0x0 BUSCLR Bus-Clear Enable 12 1 read-write COMPLETE Start back-off disable 1 1 read-write IENACK ACK not received interrupt enable 7 1 read-write IENALOST Arbitration lost interrupt enable 6 1 read-write IENCMP Transaction completed (or stop detected) interrupt enable 8 1 read-write IENMRX Receive request interrupt enable 4 1 read-write IENMTX Transmit request interrupt enable. 5 1 read-write LOOPBACK Internal loopback enable 2 1 read-write MASEN Master enable 0 1 read-write MRXDMA Enable master Rx DMA request 10 1 write-only MTXDMA Enable master Tx DMA request 11 1 write-only MXMITDEC Decrement master TX FIFO status when a byte has been transmitted 9 1 read-write STOPBUSCLR Prestop Bus-Clear 13 1 read-write STRETCHSCL Stretch SCL enable 3 1 read-write MRX Master receive data 0x8 16 read-write n 0x0 0x0 VALUE Master receive register 0 8 read-only MRXCNT Master receive data count 0x10 16 read-write n 0x0 0x0 EXTEND Extended read 8 1 read-write VALUE Receive count 0 8 read-write MSTAT Master status 0x4 16 read-write n 0x0 0x0 ALOST Arbitration lost 5 1 read-only LINEBUSY Line is busy 10 1 read-only MBUSY Master busy 6 1 read-only MRXOVR Master Receive FIFO overflow 9 1 read-only MRXREQ Master Receive request 3 1 read-only MSTOP STOP driven by this I2C Master 11 1 read-only MTXF Master Transmit FIFO status 0 2 read-only MTXREQ When read is master Transmit request when write is Clear master transmit interrupt bit 2 1 read-write MTXUNDR Master Transmit Underflow 12 1 read-only NACKADDR ACK not received in response to an address 4 1 read-only NACKDATA ACK not received in response to data write 7 1 read-only SCLFILT State of SCL Line 14 1 read-only SDAFILT State of SDA Line 13 1 read-only TCOMP Transaction complete or stop detected 8 1 read-only MTX Master transmit data 0xC 16 read-write n 0x0 0x0 VALUE Master transmit register 0 8 read-write SCTL Slave control 0x28 16 read-write n 0x0 0x0 ADR10EN Enabled 10-bit addressing 1 1 read-write EARLYTXR Early transmit request mode 5 1 read-write GCEN General call enable 2 1 read-write GCSBCLR General call status bit clear 4 1 write-only HGCEN Hardware general call enable 3 1 read-write IENREPST Repeated start interrupt enable 12 1 read-write IENSRX Slave Receive request interrupt enable 9 1 read-write IENSTOP Stop condition detected interrupt enable 8 1 read-write IENSTX Slave Transmit request interrupt enable 10 1 read-write NACK NACK next communication 7 1 read-write SLVEN Slave enable 0 1 read-write SRXDMA Enable slave Rx DMA request 13 1 read-write STXDEC Decrement Slave Tx FIFO status when a byte has been transmitted 11 1 read-write STXDMA Enable slave Tx DMA request 14 1 read-write SHCTL Shared control 0x50 16 read-write n 0x0 0x0 RST Reset START STOP detect circuit 0 1 write-only SRX Slave receive 0x30 16 read-write n 0x0 0x0 VALUE Slave receive register 0 8 read-only SSTAT Slave I2C Status/Error/IRQ 0x2C 16 read-write n 0x0 0x0 GCID General ID 8 2 read-only GCINT General call interrupt 7 1 read-only IDMAT Device ID matched 11 2 read-only NOACK Ack not generated by the slave 5 1 read-only REPSTART Repeated start and matching address 13 1 read-only SBUSY Slave busy 6 1 read-only SRXOVR Slave Receive FIFO overflow 4 1 read-only SRXREQ Slave Receive request 3 1 read-only START Start and matching address 14 1 read-only STOP Stop after start and matching address 10 1 read-only STXFSEREQ Slave Tx FIFO Status or early request 0 1 read-write STXREQ When read is slave transmit request when write is clear slave transmit interrupt bit 2 1 read-only STXUNDR Slave Transmit FIFO underflow 1 1 read-only STAT Master and slave FIFO status 0x4C 16 read-write n 0x0 0x0 MFLUSH Flush the master transmit FIFO 9 1 write-only MRXF Master receive FIFO status 6 2 read-only MTXF Master transmit FIFO status 4 2 read-only SFLUSH Flush the slave transmit FIFO 8 1 write-only SRXF Slave receive FIFO status 2 2 read-only STXF Slave transmit FIFO status 0 2 read-only STX Slave transmit 0x34 16 read-write n 0x0 0x0 VALUE Slave transmit register 0 8 read-write TCTL Timing Control Register 0x54 16 read-write n 0x0 0x0 FILTEROFF Input Filter Control 8 1 read-write THDATIN Data In Hold Start 0 5 read-write NVIC0 Cortex-M3 Interrupt Controller NVIC0 0x0 0x0 0x1000 registers n INTACT0 IRQ0..31 Active Bit 0x300 32 read-write n 0x0 0x0 VALUE IRQ0..31 Active Bit 0 32 read-write INTACT1 IRQ32..63 Active Bit 0x304 32 read-write n 0x0 0x0 VALUE IRQ32..63 Active Bit 0 32 read-write INTAFR0 Auxiliary Feature Register 0 0xD4C 32 read-write n 0x0 0x0 VALUE Auxiliary Feature Register 0 0 32 read-write INTAFSR Auxiliary Fault Status 0xD3C 32 read-write n 0x0 0x0 VALUE Auxiliary Fault Status 0 32 read-write INTAIRC Application Interrupt/Reset Control 0xD0C 32 read-write n 0x0 0x0 VALUE Application Interrupt/Reset Control 0 32 read-write INTBFAR Bus Fault Address 0xD38 32 read-write n 0x0 0x0 VALUE Bus Fault Address 0 32 read-write INTCFSR Configurable Fault Status 0xD28 32 read-write n 0x0 0x0 VALUE Configurable Fault Status 0 32 read-write INTCID0 Component Identification Bits7:0 0xFF0 32 read-write n 0x0 0x0 VALUE Component Identification Bits7:0 0 32 read-write INTCID1 Component Identification Bits15:8 0xFF4 32 read-write n 0x0 0x0 VALUE Component Identification Bits15:8 0 32 read-write INTCID2 Component Identification Bits16:23 0xFF8 32 read-write n 0x0 0x0 VALUE Component Identification Bits16:23 0 32 read-write INTCID3 Component Identification Bits24:31 0xFFC 32 read-write n 0x0 0x0 VALUE Component Identification Bits24:31 0 32 read-write INTCLRE0 IRQ0..31 Clear_Enable 0x180 32 read-write n 0x0 0x0 VALUE IRQ0..31 Clear_Enable 0 32 read-write INTCLRE1 IRQ32..63 Clear_Enable 0x184 32 read-write n 0x0 0x0 VALUE IRQ32..63 Clear_Enable 0 32 read-write INTCLRP0 IRQ0..31 Clear_Pending 0x280 32 read-write n 0x0 0x0 VALUE IRQ0..31 Clear_Pending 0 32 read-write INTCLRP1 IRQ32..63 Clear_Pending 0x284 32 read-write n 0x0 0x0 VALUE IRQ32..63 Clear_Pending 0 32 read-write INTCON0 System Control 0xD10 16 read-write n 0x0 0x0 SLEEPDEEP deep sleep flag for HIBERNATE mode 2 1 read-write SLEEPONEXIT Sleeps the core on exit from an ISR 1 1 read-write INTCON1 Configuration Control 0xD14 32 read-write n 0x0 0x0 VALUE Configuration Control 0 32 read-write INTCPID CPUID Base 0xD00 32 read-write n 0x0 0x0 VALUE CPUID Base 0 32 read-write INTDFR0 Debug Feature Register 0 0xD48 32 read-write n 0x0 0x0 VALUE Debug Feature Register 0 0 32 read-write INTDFSR Debug Fault Status 0xD30 32 read-write n 0x0 0x0 VALUE Debug Fault Status 0 32 read-write INTHFSR Hard Fault Status 0xD2C 32 read-write n 0x0 0x0 VALUE Hard Fault Status 0 32 read-write INTISAR0 ISA Feature Register 0 0xD60 32 read-write n 0x0 0x0 VALUE ISA Feature Register 0 0 32 read-write INTISAR1 ISA Feature Register 1 0xD64 32 read-write n 0x0 0x0 VALUE ISA Feature Register 1 0 32 read-write INTISAR2 ISA Feature Register 2 0xD68 32 read-write n 0x0 0x0 VALUE ISA Feature Register 2 0 32 read-write INTISAR3 ISA Feature Register 3 0xD6C 32 read-write n 0x0 0x0 VALUE ISA Feature Register 3 0 32 read-write INTISAR4 ISA Feature Register 4 0xD70 32 read-write n 0x0 0x0 VALUE ISA Feature Register 4 0 32 read-write INTMMAR Mem Manage Address 0xD34 32 read-write n 0x0 0x0 VALUE Mem Manage Address 0 32 read-write INTMMFR0 Memory Model Feature Register 0 0xD50 32 read-write n 0x0 0x0 VALUE Memory Model Feature Register 0 0 32 read-write INTMMFR1 Memory Model Feature Register 1 0xD54 32 read-write n 0x0 0x0 VALUE Memory Model Feature Register 1 0 32 read-write INTMMFR2 Memory Model Feature Register 2 0xD58 32 read-write n 0x0 0x0 VALUE Memory Model Feature Register 2 0 32 read-write INTMMFR3 Memory Model Feature Register 3 0xD5C 32 read-write n 0x0 0x0 VALUE Memory Model Feature Register 3 0 32 read-write INTNUM Interrupt Control Type 0x4 32 read-write n 0x0 0x0 VALUE Interrupt Control Type 0 32 read-write INTPFR0 Processor Feature Register 0 0xD40 32 read-write n 0x0 0x0 VALUE Processor Feature Register 0 0 32 read-write INTPFR1 Processor Feature Register 1 0xD44 32 read-write n 0x0 0x0 VALUE Processor Feature Register 1 0 32 read-write INTPID0 Peripheral Identification Bits7:0 0xFE0 32 read-write n 0x0 0x0 VALUE Peripheral Identification Bits7:0 0 32 read-write INTPID1 Peripheral Identification Bits15:8 0xFE4 32 read-write n 0x0 0x0 VALUE Peripheral Identification Bits15:8 0 32 read-write INTPID2 Peripheral Identification Bits16:23 0xFE8 32 read-write n 0x0 0x0 VALUE Peripheral Identification Bits16:23 0 32 read-write INTPID3 Peripheral Identification Bits24:31 0xFEC 32 read-write n 0x0 0x0 VALUE Peripheral Identification Bits24:31 0 32 read-write INTPID4 Peripheral Identification Register 4 0xFD0 32 read-write n 0x0 0x0 VALUE Peripheral Identification Register 4 0 32 read-write INTPID5 Peripheral Identification Register 5 0xFD4 32 read-write n 0x0 0x0 VALUE Peripheral Identification Register 5 0 32 read-write INTPID6 Peripheral Identification Register 6 0xFD8 32 read-write n 0x0 0x0 VALUE Peripheral Identification Register 6 0 32 read-write INTPID7 Peripheral Identification Register 7 0xFDC 32 read-write n 0x0 0x0 VALUE Peripheral Identification Register 7 0 32 read-write INTPRI0 IRQ0..3 Priority 0x400 32 read-write n 0x0 0x0 VALUE IRQ0..3 Priority 0 32 read-write INTPRI1 IRQ4..7 Priority 0x404 32 read-write n 0x0 0x0 VALUE IRQ4..7 Priority 0 32 read-write INTPRI10 IRQ40..43 Priority 0x428 32 read-write n 0x0 0x0 VALUE IRQ40..43 Priority 0 32 read-write INTPRI2 IRQ8..11 Priority 0x408 32 read-write n 0x0 0x0 VALUE IRQ8..11 Priority 0 32 read-write INTPRI3 IRQ12..15 Priority 0x40C 32 read-write n 0x0 0x0 VALUE IRQ12..15 Priority 0 32 read-write INTPRI4 IRQ16..19 Priority 0x410 32 read-write n 0x0 0x0 VALUE IRQ16..19 Priority 0 32 read-write INTPRI5 IRQ20..23 Priority 0x414 32 read-write n 0x0 0x0 VALUE IRQ20..23 Priority 0 32 read-write INTPRI6 IRQ24..27 Priority 0x418 32 read-write n 0x0 0x0 VALUE IRQ24..27 Priority 0 32 read-write INTPRI7 IRQ28..31 Priority 0x41C 32 read-write n 0x0 0x0 VALUE IRQ28..31 Priority 0 32 read-write INTPRI8 IRQ32..35 Priority 0x420 32 read-write n 0x0 0x0 VALUE IRQ32..35 Priority 0 32 read-write INTPRI9 IRQ36..39 Priority 0x424 32 read-write n 0x0 0x0 VALUE IRQ36..39 Priority 0 32 read-write INTSETE0 IRQ0..31 Set_Enable 0x100 32 read-write n 0x0 0x0 VALUE IRQ0..31 Set_Enable 0 32 read-write INTSETE1 IRQ32..63 Set_Enable 0x104 32 read-write n 0x0 0x0 VALUE IRQ32..63 Set_Enable 0 32 read-write INTSETP0 IRQ0..31 Set_Pending 0x200 32 read-write n 0x0 0x0 VALUE IRQ0..31 Set_Pending 0 32 read-write INTSETP1 IRQ32..63 Set_Pending 0x204 32 read-write n 0x0 0x0 VALUE IRQ32..63 Set_Pending 0 32 read-write INTSHCSR System Handler Control and State 0xD24 32 read-write n 0x0 0x0 VALUE System Handler Control and State 0 32 read-write INTSHPRIO0 System Handlers 4-7 Priority 0xD18 32 read-write n 0x0 0x0 VALUE System Handlers 4-7 Priority 0 32 read-write INTSHPRIO1 System Handlers 8-11 Priority 0xD1C 32 read-write n 0x0 0x0 VALUE System Handlers 8-11 Priority 0 32 read-write INTSHPRIO3 System Handlers 12-15 Priority 0xD20 32 read-write n 0x0 0x0 VALUE System Handlers 12-15 Priority 0 32 read-write INTSTA Interrupt Control State 0xD04 32 read-write n 0x0 0x0 VALUE Interrupt Control State 0 32 read-write INTTRGI Software Trigger Interrupt Register 0xF00 32 read-write n 0x0 0x0 VALUE Software Trigger Interrupt Register 0 32 read-write INTVEC Vector Table Offset 0xD08 32 read-write n 0x0 0x0 VALUE Vector Table Offset 0 32 read-write STKCAL Systick Calibration Value 0x1C 32 read-write n 0x0 0x0 VALUE Systick Calibration Value 0 32 read-write STKLD Systick Reload Value 0x14 32 read-write n 0x0 0x0 VALUE Systick Reload Value 0 32 read-write STKSTA Systick Control and Status 0x10 32 read-write n 0x0 0x0 VALUE Systick Control and Status 0 32 read-write STKVAL Systick Current Value 0x18 32 read-write n 0x0 0x0 VALUE Systick Current Value 0 32 read-write PMG0 Power Management PMG0 0x0 0x0 0x50 registers n PMG0_VREG_OVR Voltage Regulator (VREG) Overvoltage 6 PMG0_BATT_RANGE Battery Voltage (VBAT) Out of Range 7 CTL1 HPBUCK control 0x44 32 read-write n 0x0 0x0 HPBUCKEN Enable HP Buck 0 1 read-write IEN Power Supply Monitor Interrupt Enable 0x0 32 read-write n 0x0 0x0 IENBAT Interrupt enable for VBAT range 10 1 read-write RANGEBAT Battery Monitor Range 8 2 read-write region1 Configure to generate interrupt if VBAT > 2.75V 0 region2 Configure to generate interrupt if VBAT between 2.75V - 1.6V 1 region3 Configure to generate interrupt if VBAT between 2.3V - 1.6V 2 NA N/A 3 VBAT Enable Interrupt for VBAT 0 1 read-write VREGOVR Enable Interrupt when VREG over-voltage: over- 1.32V 2 1 read-write VREGUNDR Enable Interrupt when VREG under-voltage: below 1V 1 1 read-write PSM_STAT Power supply monitor status 0x4 32 read-write n 0x0 0x0 RANGE1 VBAT range1 (> 2.75v) 8 1 read-write RANGE2 VBAT range2 (2.75v - 2.3v) 9 1 read-write RANGE3 VBAT range3 (2.3v - 1.6v) 10 1 read-write RORANGE1 VBAT range1 (> 2.75v) 13 1 read-only batstat1 VBAT NOT in the range specified 0 batstat0 VBAT in the range specified 1 RORANGE2 VBAT range2 (2.75v - 2.3v) 14 1 read-only RORANGE3 VBAT range3 (2.3v - 1.6v) 15 1 read-only VBATUNDR Status bit indicating an Alarm that battery is below 1.8V. 0 1 read-write VREGOVR Status bit for alarm indicating Overvoltage for VREG 2 1 read-write VREGUNDR Status bit for Alarm indicating VREG is below 1V. 1 1 read-write WICENACK WIC Enable Acknowledge from Cortex 7 1 read-only PWRKEY Key protection for PWRMOD and SRAMRET 0xC 32 read-write n 0x0 0x0 VALUE Power control key register 0 16 write-only PWRMOD Power Mode Register 0x8 32 read-write n 0x0 0x0 MODE Power Mode Bits 0 2 read-write FLEXI FLEXI Mode 0 HIBERNATE HIBERNATE Mode 2 SHUTDOWN SHUTDOWN Mode 3 MONVBATN Monitor VBAT during HIBERNATE Mode. Monitors VBAT by default 3 1 read-write RST_STAT Reset status 0x40 32 read-write n 0x0 0x0 EXTRST External reset 1 1 read-write POR Power-on reset 0 1 read-write PORSRC Power on reset Source (pmg_rst_src) 4 2 read-only FAILSAFE_HV POR triggered because VBAT drops below Fail Safe 0 RST_VBAT POR trigger because VBAT supply (VBAT<1.7v) 1 RST_VREG POR triggered because VDD supply (VDD < 1.08v) 2 FAILSAFE_LV POR triggered because VREG drops below Fail Safe 3 SWRST Software reset 3 1 read-write WDRST Watchdog timeout 2 1 read-write SHDN_STAT SHUTDOWN Status Register 0x10 32 read-write n 0x0 0x0 EXTINT0 Interrupt from External Interrupt 0 0 1 read-only EXTINT1 Interrupt from External Interrupt 1 1 1 read-only EXTINT2 Interrupt from External Interrupt 2 2 1 read-only RTC Interrupt from RTC 3 1 read-only SRAMRET Control for Retention SRAM during HIBERNATE Mode 0x14 32 read-write n 0x0 0x0 BNK1EN Enable retention bank 1 (8kB) 0 1 read-write BNK2EN Enable retention bank 2 (16kB) 1 1 read-write PMG0_TST Power Management PMG0_TST 0x0 0x0 0x50 registers n CLR_LATCH_GPIOS CLEAR GPIO AFTER SHUTDOWN MODE 0x68 16 read-write n 0x0 0x0 VALUE Writing 0x58FA creates a pulse to clear the latches for the GPIOs 0 16 write-only SCRPAD_3V_RD SCRATCH PAD SAVED IN BATTERY DOMAIN 0x70 32 read-write n 0x0 0x0 DATA Read Only register. Reading the scratch pad stored in shutdown mode 0 32 read-only SCRPAD_IMG SCRATCH PAD IMAGE 0x6C 32 read-write n 0x0 0x0 DATA Anything written to this register will be saved in 3V when going to shutdown mode 0 32 read-write SRAM_CTL Control for SRAM parity and instruction SRAM 0x60 32 read-write n 0x0 0x0 ABTINIT Abort current initialization. Self-cleared 15 1 read-write AUTOINIT Automatic initialization on wake up from Hibernate mode 14 1 read-write BNK0EN Enable initialization 0 1 read-write BNK1EN Enable initialization 1 1 read-write BNK2EN Enable initialization 2 1 read-write BNK3EN Enable initialization 3 1 read-write BNK4EN Enable initialization 4 1 read-write BNK5EN Enable initialization 5 1 read-write INSTREN Enables instruction SRAM 31 1 read-write PENBNK0 Enable parity check 16 1 read-write PENBNK1 Enable parity check 17 1 read-write PENBNK2 Enable parity check 18 1 read-write PENBNK3 Enable parity check 19 1 read-write PENBNK4 Enable parity check 20 1 read-write PENBNK5 Enable parity check 21 1 read-write STARTINIT Write one to trigger initialization. Self-cleared 13 1 read-write SRAM_INITSTAT Initialization Status Register 0x64 32 read-write n 0x0 0x0 BNK0 0:Not initialized 1:Initialization completed 0 1 read-only BNK1 0:Not initialized 1:Initialization completed 1 1 read-only BNK2 0:Not initialized 1:Initialization completed 2 1 read-only BNK3 0:Not initialized 1:Initialization completed 3 1 read-only BNK4 0:Not initialized 1:Initialization completed 4 1 read-only BNK5 0:Not initialized 1:Initialization completed 5 1 read-only RNG0 Random Number Generator RNG0 0x0 0x0 0x100 registers n RNG0_EVT RNG0_EVT 44 CTL RNG Control Register 0x0 16 read-write n 0x0 0x0 EN RNG Enable 0 1 read-write DISABLE Disable the RNG 0 ENABLE Enable the RNG 1 SINGLE Generate a single number 3 1 read-write WORD Buffer Word 0 SINGLE Single Byte 1 DATA RNG Data Register 0xC 32 read-write n 0x0 0x0 BUFF Buffer for RNG data 8 24 read-only VALUE Value of the CRC accumulator 0 8 read-only LEN RNG Sample Length Register 0x4 16 read-write n 0x0 0x0 PRESCALE Prescaler for the sample counter 12 4 read-write RELOAD Reload value for the sample counter 0 12 read-write OSCCNT Oscillator Count 0x10 32 read-write n 0x0 0x0 VALUE Oscillator count 0 28 read-only OSCDIFF0 Oscillator Difference 0x14 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF1 Oscillator Difference 0x15 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF2 Oscillator Difference 0x16 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF3 Oscillator Difference 0x17 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF[0] Oscillator Difference 0x28 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF[1] Oscillator Difference 0x3D 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF[2] Oscillator Difference 0x53 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only OSCDIFF[3] Oscillator Difference 0x6A 8 read-write n 0x0 0x0 DELTA Oscillator Count difference 0 8 read-only STAT RNG Status Register 0x8 16 read-write n 0x0 0x0 RNRDY Random number ready 0 1 read-write STUCK Sampled data stuck high or low 1 1 read-write RTC0 Real-Time Clock RTC0 0x0 0x0 0x100 registers n RTC0_EVT RTC0 Event 8 ALM0 RTC Alarm 0 0x14 16 read-write n 0x0 0x0 VALUE Lower 16 prescaled (that is, non-fractional) bits of the RTC alarm target time 0 16 read-write ALM1 RTC Alarm 1 0x18 16 read-write n 0x0 0x0 VALUE Upper 16 prescaled (non-fractional) bits of the RTC alarm target time 0 16 read-write ALM2 RTC Alarm 2 0x44 16 read-write n 0x0 0x0 VALUE Fractional (non-prescaled) bits of the RTC alarm target time 0 15 read-write CNT0 RTC Count 0 0xC 16 read-write n 0x0 0x0 VALUE Lower 16 prescaled (non-fractional) bits of the RTC real-time count 0 16 read-write CNT1 RTC Count 1 0x10 16 read-write n 0x0 0x0 VALUE Upper 16 prescaled (non-fractional) bits of the RTC real-time count 0 16 read-write CNT2 RTC Count 2 0x40 16 read-write n 0x0 0x0 VALUE Fractional bits of the RTC real-time count 0 15 read-only CR0 RTC Control 0 0x0 16 read-write n 0x0 0x0 ALMEN Enable the RTC alarm (absolute) operation 1 1 read-write ALMINTEN Enable sourced alarm interrupts to the CPU 2 1 read-write CNTEN Global enable for the RTC 0 1 read-write ISOINTEN Enable RTC power-domain isolation sourced interrupts to the CPU when isolation of the RTC power domain is activated and subsequently de-activated 12 1 read-write MOD60ALM Periodic, modulo-60 alarm time in prescaled RTC time units beyond a modulo-60 boundary 5 6 read-write Example_1_Thirty_time_units_decimal Example of setting a modulo-60 periodic interrupt from the RTC to be issued to the CPU at 30 time units past a modulo-60 boundary. 30 Example_2_FiftyFive_time_units_decimal Example of setting a modulo-60 periodic interrupt from the RTC to be issued to the CPU at 55 time units past a modulo-60 boundary. 55 MOD60ALMEN Enable RTC modulo-60 counting of time past a modulo-60 boundary 4 1 read-write MOD60ALMINTEN Enable periodic Modulo-60 RTC alarm sourced interrupts to the CPU 11 1 read-write TRMEN Enable RTC digital trimming 3 1 read-write WPNDERRINTEN Enable Write pending error sourced interrupts to the CPU when an RTC register-write pending error occurs 13 1 read-write WPNDINTEN Enable Write Pending sourced interrupts to the CPU 15 1 read-write WSYNCINTEN Enable Write synchronization sourced interrupts to the CPU 14 1 read-write CR1 RTC Control 1 0x28 16 read-write n 0x0 0x0 CNTINTEN Enable for the RTC count interrupt source 0 1 read-write CNTMOD60ROLLINTEN Enable for the RTC modulo-60 count roll-over interrupt source in RTC Status 2 Register 4 1 read-write CNTROLLINTEN Enable for the RTC count roll-over interrupt source in RTC Status 2 Register 3 1 read-write PRESCALE2EXP Prescale power of 2 division factor for the RTC base clock 5 4 read-write PSINTEN Enable for the prescaled, modulo-1 interrupt source 1 1 read-write RTCTRMINTEN Enable for the RTC Trim interrupt source 2 1 read-write CR2IC RTC Control 2 for Configuring Input Capture Channels 0x4C 16 read-write n 0x0 0x0 RTCIC0EN Enable for the RTC Input Capture Channel 0 0 1 read-write RTCIC0IRQEN Interrupt Enable for the RTC Input Capture Channel 0 10 1 read-write RTCIC0LH Polarity of the active-going capture edge for the RTC Input Capture Channel 0 5 1 read-write RTCIC2EN Enable for the RTC Input Capture Channel 2 2 1 read-write RTCIC2IRQEN Interrupt Enable for the RTC Input Capture Channel 2 12 1 read-write RTCIC2LH Polarity of the active-going capture edge for the RTC Input Capture Channel 2 7 1 read-write RTCIC3EN Enable for the RTC Input Capture Channel 3 3 1 read-write RTCIC3IRQEN Interrupt Enable for the RTC Input Capture Channel 3 13 1 read-write RTCIC3LH Polarity of the active-going capture edge for the RTC Input Capture Channel 3 8 1 read-write RTCIC4EN Enable for the RTC Input Capture Channel 4 4 1 read-write RTCIC4IRQEN Interrupt Enable for the RTC Input Capture Channel 4 14 1 read-write RTCIC4LH Polarity of the active-going capture edge for the RTC Input Capture Channel 4 9 1 read-write RTCICOWUSEN Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels 15 1 read-write CR3OC RTC Control 3 for Configuring Output Compare Channel 0x50 16 read-write n 0x0 0x0 RTCOC1EN Enable for Output Compare Channel 1 1 1 read-write RTCOC1IRQEN Interrupt Enable for Output Compare Channel 1 9 1 read-write CR4OC RTC Control 4 for Configuring Output Compare Channel 0x54 16 read-write n 0x0 0x0 RTCOC1ARLEN Enable for auto-reloading when output compare match occurs 9 1 read-write RTCOC1MSKEN Enable for thermometer-code masking of the Output Compare 1 Channel 1 1 read-write EN000 Do not apply a mask to the 16-bit Output Compare channel OC1. 0 EN001 Apply a thermometer-decoded mask to the 16-bit Output Compare channel OC1 provided that channel is enabled via CR3OC:RTCOC1EN 1 FRZCNT RTC Freeze Count 0x90 16 read-write n 0x0 0x0 RTCFRZCNT RTC Freeze Count 0 16 read-only GWY RTC Gateway 0x20 16 read-write n 0x0 0x0 SWKEY Software-keyed command issued by the CPU 0 16 write-only IC2 RTC Input Capture Channel 2 0x64 16 read-write n 0x0 0x0 RTCIC2 RTC Input Capture Channel 2 0 16 read-only IC3 RTC Input Capture Channel 3 0x68 16 read-write n 0x0 0x0 RTCIC3 RTC Input Capture Channel 3 0 16 read-only IC4 RTC Input Capture Channel 4 0x6C 16 read-write n 0x0 0x0 RTCIC4 RTC Input Capture Channel 4 0 16 read-only MOD RTC Modulo 0x3C 16 read-write n 0x0 0x0 CNT0_4TOZERO Mirror of RTC Count 0 Register [4:0] 11 5 read-only CNTMOD60 Modulo-60 value of prescaled RTC Count 1 and RTC Count 0 Registers 0 6 read-only INCR Most recent increment value added to the RTC Count in RTC Count 1 and RTC Count 0 Registers 6 4 read-only TRMBDY Trim boundary indicator that the most recent RTC count increment has coincided with trimming of the count value 10 1 read-only OC1 RTC Output Compare Channel 1 0x70 16 read-write n 0x0 0x0 RTCOC1 RTC Output Compare 1 Channel. Scheduled alarm target time with optional auto-reload 0 16 read-write OC1ARL RTC Auto-Reload for Output Compare Channel 1 0x5C 16 read-write n 0x0 0x0 RTCOC1ARL Auto-reload value when output compare match occurs 0 16 read-write OC1TGT RTC Output Compare Channel 1 Target 0x8C 16 read-write n 0x0 0x0 RTCOC1TGT Current, cumulative target time for Output Compare Channel 1, taking account of any auto-reloading 0 16 read-only OCMSK RTC Masks for Output Compare Channel 0x58 16 read-write n 0x0 0x0 RTCOCMSK Concatenation of thermometer-encoded masks for the 16-bit output compare channels 0 16 read-write SNAP0 RTC Snapshot 0 0x30 16 read-write n 0x0 0x0 VALUE Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 0 Register 0 16 read-only SNAP1 RTC Snapshot 1 0x34 16 read-write n 0x0 0x0 VALUE Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 1 Register 0 16 read-only SNAP2 RTC Snapshot 2 0x38 16 read-write n 0x0 0x0 VALUE Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 2 Register 0 15 read-only SR0 RTC Status 0 0x4 16 read-write n 0x0 0x0 ALMINT Alarm interrupt source 1 1 read-write ISOENB Visibility status of 32 kHz sourced registers, taking account of power-domain isolation 14 1 read-only ISOINT RTC power-domain isolation interrupt source 3 1 read-write MOD60ALMINT Modulo-60 RTC alarm interrupt source 2 1 read-write WPNDERRINT Write pending error interrupt source 4 1 read-write WPNDINT Write pending interrupt 6 1 read-write WSYNCALM0 Synchronization status of posted writes to RTC Alarm 0 Register 11 1 read-only WSYNCALM1 Synchronization status of posted writes to RTC Alarm 1 Register 12 1 read-only WSYNCCNT0 Synchronization status of posted writes to RTC Count 0 Register 9 1 read-only WSYNCCNT1 Synchronization status of posted writes to RTC Count 1 Register 10 1 read-only WSYNCCR0 Synchronization status of posted writes to RTC Control 0 Register 7 1 read-only WSYNCINT Write synchronization interrupt 5 1 read-write WSYNCSR0 Synchronization status of posted clearances to interrupt sources in RTC Status 0 Register 8 1 read-only WSYNCTRM Synchronization status of posted writes to RTC Trim Register 13 1 read-only SR1 RTC Status 1 0x8 16 read-write n 0x0 0x0 WPNDALM0 Pending status of posted writes to RTC ALARM 0 Register 11 1 read-only WPNDALM1 Pending status of posted writes to RTC ALARM 1 Register 12 1 read-only WPNDCNT0 Pending status of posted writes to RTC Count 0 Register 9 1 read-only WPNDCNT1 Pending status of posted writes to RTC Count 1 Register 10 1 read-only WPNDCR0 Pending status of posted writes to RTC Control 0 Register 7 1 read-only WPNDSR0 Pending status of posted clearances of interrupt sources in RTC Status 0 Register 8 1 read-only WPNDTRM Pending status of posted writes to RTC Trim Register 13 1 read-only SR2 RTC Status 2 0x2C 16 read-write n 0x0 0x0 CNTINT RTC count interrupt source 0 1 read-write CNTMOD60ROLL RTC count modulo-60 roll-over 6 1 read-only CNTMOD60ROLLINT RTC modulo-60 count roll-over interrupt source 4 1 read-write CNTROLL RTC count roll-over 5 1 read-only CNTROLLINT RTC count roll-over interrupt source 3 1 read-write PSINT RTC prescaled, modulo-1 boundary interrupt source 1 1 read-write TRMBDYMIR Mirror of the RTCTRMBDY field of RTC Modulo Register 7 1 read-only TRMINT RTC Trim interrupt source 2 1 read-write WPNDALM2MIR Pending status of posted writes to RTC Alarm 2 Register 13 1 read-only WPNDCR1MIR Pending status of posted writes to RTC Control 1 Register 12 1 read-only WSYNCALM2MIR Synchronization status of posted writes to RTC Alarm 2 Register 15 1 read-only WSYNCCR1MIR Synchronization status of posted writes to RTC Control 1 Register 14 1 read-only SR3 RTC Status 3 0x48 16 read-write n 0x0 0x0 ALMINTMIR Read-only mirror of the ALMINT interrupt source in RTC Status 0 Register, acting as RTCOC0IRQ 8 1 read-only RTCIC0IRQ Sticky Interrupt Source for the RTC Input Capture Channel 0 0 1 read-write RTCIC2IRQ Sticky Interrupt Source for the RTC Input Capture Channel 2 2 1 read-write RTCIC3IRQ Sticky Interrupt Source for the RTC Input Capture Channel 3 3 1 read-write RTCIC4IRQ Sticky Interrupt Source for the RTC Input Capture Channel 4 4 1 read-write RTCOC1IRQ Sticky Interrupt Source for Output Compare Channel 1 9 1 read-write SR4 RTC Status 4 0x80 16 read-write n 0x0 0x0 RSYNCIC0 Synchronization status of posted reads of RTC Input Channel 0 10 1 read-only RSYNCIC2 Synchronization status of posted reads of RTC Input Channel 2 12 1 read-only RSYNCIC3 Synchronization status of posted reads of RTC Input Channel 3 13 1 read-only RSYNCIC4 Synchronization status of posted reads of RTC Input Channel 4 14 1 read-only WSYNCCR2IC Synchronization status of posted writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WSYNCCR3OC Synchronization status of posted writes to RTC Control 3 for Configuring Output Compare Channel Register 2 1 read-only WSYNCCR4OC Synchronization status of posted writes to RTC Control 4 for Configuring Output Compare Channel Register 3 1 read-only WSYNCOC1 Synchronization status of posted writes to RTC Output Compare Channel 1 Register 6 1 read-only WSYNCOC1ARL Synchronization status of posted writes to RTC Auto-Reload for Output Compare Channel 1 Register 5 1 read-only WSYNCOCMSK Synchronization status of posted writes to RTC Masks for Output Compare Channel Register 4 1 read-only WSYNCSR3 Synchronization status of posted clearances to interrupt sources in RTC Status 3 Register 0 1 read-only SR5 RTC Status 5 0x84 16 read-write n 0x0 0x0 RPENDIC0 Pending status of posted reads of RTC Input Channel 0 10 1 read-only RPENDIC2 Pending status of posted reads of RTC Input Channel 2 12 1 read-only RPENDIC3 Pending status of posted reads of RTC Input Channel 3 13 1 read-only RPENDIC4 Pending status of posted reads of RTC Input Channel 4 14 1 read-only WPENDCR2IC Pending status of posted writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WPENDCR3OC Pending status of posted writes to RTC Control 3 for Configuring Output Compare Channel Register 2 1 read-only WPENDCR4OC Pending status of posted writes to RTC Control 4 for Configuring Output Compare Channel Register 3 1 read-only WPENDOC1 Pending status of posted writes to Output Compare Channel 1 6 1 read-only WPENDOC1ARL Pending status of posted writes to RTC Auto-Reload for Output Compare Channel 1 Register 5 1 read-only WPENDOCMSK Pending status of posted writes to RTC Masks for Output Compare Channel Register 4 1 read-only WPNDSR0 Pending status of posted clearances of interrupt sources in RTC Status 3 Register 0 1 read-only SR6 RTC Status 6 0x88 16 read-write n 0x0 0x0 RTCFRZCNTPTR Pointer for the triple-read sequence of the RTC Freeze Count MMR 9 2 read-only RTCIC0SNAP Confirmation that RTC Snapshot 0, 1, 2 registers reflect the value of RTC Input Capture Channel 0 8 1 read-only RTCIC0UNR Sticky unread status of the RTC Input Capture Channel 0 0 1 read-only RTCIC2UNR Sticky unread status of the RTC Input Capture Channel 2 2 1 read-only RTCIC3UNR Sticky unread status of the RTC Input Capture Channel 3 3 1 read-only RTCIC4UNR Sticky unread status of the RTC Input Capture Channel 4 4 1 read-only TRM RTC Trim 0x1C 16 read-write n 0x0 0x0 ADD Trim Polarity 3 1 read-write IVL Trim interval in prescaled RTC time units 4 2 read-write IVL2EXPMIN Minimum power-of-two interval of prescaled RTC time units, which RTC Trim Register can select 6 4 read-write VALUE Trim value in prescaled RTC time units to be added or subtracted from the RTC count at the end of a periodic interval selected by RTC Trim Register 0 3 read-write RTC1 Real-Time Clock RTC0 0x0 0x0 0x100 registers n RTC1_EVT Event 0 ALM0 RTC Alarm 0 0x14 16 read-write n 0x0 0x0 VALUE Lower 16 prescaled (that is, non-fractional) bits of the RTC alarm target time 0 16 read-write ALM1 RTC Alarm 1 0x18 16 read-write n 0x0 0x0 VALUE Upper 16 prescaled (non-fractional) bits of the RTC alarm target time 0 16 read-write ALM2 RTC Alarm 2 0x44 16 read-write n 0x0 0x0 VALUE Fractional (non-prescaled) bits of the RTC alarm target time 0 15 read-write CNT0 RTC Count 0 0xC 16 read-write n 0x0 0x0 VALUE Lower 16 prescaled (non-fractional) bits of the RTC real-time count 0 16 read-write CNT1 RTC Count 1 0x10 16 read-write n 0x0 0x0 VALUE Upper 16 prescaled (non-fractional) bits of the RTC real-time count 0 16 read-write CNT2 RTC Count 2 0x40 16 read-write n 0x0 0x0 VALUE Fractional bits of the RTC real-time count 0 15 read-only CR0 RTC Control 0 0x0 16 read-write n 0x0 0x0 ALMEN Enable the RTC alarm (absolute) operation 1 1 read-write ALMINTEN Enable sourced alarm interrupts to the CPU 2 1 read-write CNTEN Global enable for the RTC 0 1 read-write ISOINTEN Enable RTC power-domain isolation sourced interrupts to the CPU when isolation of the RTC power domain is activated and subsequently de-activated 12 1 read-write MOD60ALM Periodic, modulo-60 alarm time in prescaled RTC time units beyond a modulo-60 boundary 5 6 read-write Example_1_Thirty_time_units_decimal Example of setting a modulo-60 periodic interrupt from the RTC to be issued to the CPU at 30 time units past a modulo-60 boundary. 30 Example_2_FiftyFive_time_units_decimal Example of setting a modulo-60 periodic interrupt from the RTC to be issued to the CPU at 55 time units past a modulo-60 boundary. 55 MOD60ALMEN Enable RTC modulo-60 counting of time past a modulo-60 boundary 4 1 read-write MOD60ALMINTEN Enable periodic Modulo-60 RTC alarm sourced interrupts to the CPU 11 1 read-write TRMEN Enable RTC digital trimming 3 1 read-write WPNDERRINTEN Enable Write pending error sourced interrupts to the CPU when an RTC register-write pending error occurs 13 1 read-write WPNDINTEN Enable Write Pending sourced interrupts to the CPU 15 1 read-write WSYNCINTEN Enable Write synchronization sourced interrupts to the CPU 14 1 read-write CR1 RTC Control 1 0x28 16 read-write n 0x0 0x0 CNTINTEN Enable for the RTC count interrupt source 0 1 read-write CNTMOD60ROLLINTEN Enable for the RTC modulo-60 count roll-over interrupt source in RTC Status 2 Register 4 1 read-write CNTROLLINTEN Enable for the RTC count roll-over interrupt source in RTC Status 2 Register 3 1 read-write PRESCALE2EXP Prescale power of 2 division factor for the RTC base clock 5 4 read-write PSINTEN Enable for the prescaled, modulo-1 interrupt source 1 1 read-write RTCTRMINTEN Enable for the RTC Trim interrupt source 2 1 read-write CR2IC RTC Control 2 for Configuring Input Capture Channels 0x4C 16 read-write n 0x0 0x0 RTCIC0EN Enable for the RTC Input Capture Channel 0 0 1 read-write RTCIC0IRQEN Interrupt Enable for the RTC Input Capture Channel 0 10 1 read-write RTCIC0LH Polarity of the active-going capture edge for the RTC Input Capture Channel 0 5 1 read-write RTCIC2EN Enable for the RTC Input Capture Channel 2 2 1 read-write RTCIC2IRQEN Interrupt Enable for the RTC Input Capture Channel 2 12 1 read-write RTCIC2LH Polarity of the active-going capture edge for the RTC Input Capture Channel 2 7 1 read-write RTCIC3EN Enable for the RTC Input Capture Channel 3 3 1 read-write RTCIC3IRQEN Interrupt Enable for the RTC Input Capture Channel 3 13 1 read-write RTCIC3LH Polarity of the active-going capture edge for the RTC Input Capture Channel 3 8 1 read-write RTCIC4EN Enable for the RTC Input Capture Channel 4 4 1 read-write RTCIC4IRQEN Interrupt Enable for the RTC Input Capture Channel 4 14 1 read-write RTCIC4LH Polarity of the active-going capture edge for the RTC Input Capture Channel 4 9 1 read-write RTCICOWUSEN Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels 15 1 read-write CR3OC RTC Control 3 for Configuring Output Compare Channel 0x50 16 read-write n 0x0 0x0 RTCOC1EN Enable for Output Compare Channel 1 1 1 read-write RTCOC1IRQEN Interrupt Enable for Output Compare Channel 1 9 1 read-write CR4OC RTC Control 4 for Configuring Output Compare Channel 0x54 16 read-write n 0x0 0x0 RTCOC1ARLEN Enable for auto-reloading when output compare match occurs 9 1 read-write RTCOC1MSKEN Enable for thermometer-code masking of the Output Compare 1 Channel 1 1 read-write EN000 Do not apply a mask to the 16-bit Output Compare channel OC1. 0 EN001 Apply a thermometer-decoded mask to the 16-bit Output Compare channel OC1 provided that channel is enabled via CR3OC:RTCOC1EN 1 FRZCNT RTC Freeze Count 0x90 16 read-write n 0x0 0x0 RTCFRZCNT RTC Freeze Count 0 16 read-only GWY RTC Gateway 0x20 16 read-write n 0x0 0x0 SWKEY Software-keyed command issued by the CPU 0 16 write-only IC2 RTC Input Capture Channel 2 0x64 16 read-write n 0x0 0x0 RTCIC2 RTC Input Capture Channel 2 0 16 read-only IC3 RTC Input Capture Channel 3 0x68 16 read-write n 0x0 0x0 RTCIC3 RTC Input Capture Channel 3 0 16 read-only IC4 RTC Input Capture Channel 4 0x6C 16 read-write n 0x0 0x0 RTCIC4 RTC Input Capture Channel 4 0 16 read-only MOD RTC Modulo 0x3C 16 read-write n 0x0 0x0 CNT0_4TOZERO Mirror of RTC Count 0 Register [4:0] 11 5 read-only CNTMOD60 Modulo-60 value of prescaled RTC Count 1 and RTC Count 0 Registers 0 6 read-only INCR Most recent increment value added to the RTC Count in RTC Count 1 and RTC Count 0 Registers 6 4 read-only TRMBDY Trim boundary indicator that the most recent RTC count increment has coincided with trimming of the count value 10 1 read-only OC1 RTC Output Compare Channel 1 0x70 16 read-write n 0x0 0x0 RTCOC1 RTC Output Compare 1 Channel. Scheduled alarm target time with optional auto-reload 0 16 read-write OC1ARL RTC Auto-Reload for Output Compare Channel 1 0x5C 16 read-write n 0x0 0x0 RTCOC1ARL Auto-reload value when output compare match occurs 0 16 read-write OC1TGT RTC Output Compare Channel 1 Target 0x8C 16 read-write n 0x0 0x0 RTCOC1TGT Current, cumulative target time for Output Compare Channel 1, taking account of any auto-reloading 0 16 read-only OCMSK RTC Masks for Output Compare Channel 0x58 16 read-write n 0x0 0x0 RTCOCMSK Concatenation of thermometer-encoded masks for the 16-bit output compare channels 0 16 read-write SNAP0 RTC Snapshot 0 0x30 16 read-write n 0x0 0x0 VALUE Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 0 Register 0 16 read-only SNAP1 RTC Snapshot 1 0x34 16 read-write n 0x0 0x0 VALUE Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 1 Register 0 16 read-only SNAP2 RTC Snapshot 2 0x38 16 read-write n 0x0 0x0 VALUE Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky snapshot of RTC Count 2 Register 0 15 read-only SR0 RTC Status 0 0x4 16 read-write n 0x0 0x0 ALMINT Alarm interrupt source 1 1 read-write ISOENB Visibility status of 32 kHz sourced registers, taking account of power-domain isolation 14 1 read-only ISOINT RTC power-domain isolation interrupt source 3 1 read-write MOD60ALMINT Modulo-60 RTC alarm interrupt source 2 1 read-write WPNDERRINT Write pending error interrupt source 4 1 read-write WPNDINT Write pending interrupt 6 1 read-write WSYNCALM0 Synchronization status of posted writes to RTC Alarm 0 Register 11 1 read-only WSYNCALM1 Synchronization status of posted writes to RTC Alarm 1 Register 12 1 read-only WSYNCCNT0 Synchronization status of posted writes to RTC Count 0 Register 9 1 read-only WSYNCCNT1 Synchronization status of posted writes to RTC Count 1 Register 10 1 read-only WSYNCCR0 Synchronization status of posted writes to RTC Control 0 Register 7 1 read-only WSYNCINT Write synchronization interrupt 5 1 read-write WSYNCSR0 Synchronization status of posted clearances to interrupt sources in RTC Status 0 Register 8 1 read-only WSYNCTRM Synchronization status of posted writes to RTC Trim Register 13 1 read-only SR1 RTC Status 1 0x8 16 read-write n 0x0 0x0 WPNDALM0 Pending status of posted writes to RTC ALARM 0 Register 11 1 read-only WPNDALM1 Pending status of posted writes to RTC ALARM 1 Register 12 1 read-only WPNDCNT0 Pending status of posted writes to RTC Count 0 Register 9 1 read-only WPNDCNT1 Pending status of posted writes to RTC Count 1 Register 10 1 read-only WPNDCR0 Pending status of posted writes to RTC Control 0 Register 7 1 read-only WPNDSR0 Pending status of posted clearances of interrupt sources in RTC Status 0 Register 8 1 read-only WPNDTRM Pending status of posted writes to RTC Trim Register 13 1 read-only SR2 RTC Status 2 0x2C 16 read-write n 0x0 0x0 CNTINT RTC count interrupt source 0 1 read-write CNTMOD60ROLL RTC count modulo-60 roll-over 6 1 read-only CNTMOD60ROLLINT RTC modulo-60 count roll-over interrupt source 4 1 read-write CNTROLL RTC count roll-over 5 1 read-only CNTROLLINT RTC count roll-over interrupt source 3 1 read-write PSINT RTC prescaled, modulo-1 boundary interrupt source 1 1 read-write TRMBDYMIR Mirror of the RTCTRMBDY field of RTC Modulo Register 7 1 read-only TRMINT RTC Trim interrupt source 2 1 read-write WPNDALM2MIR Pending status of posted writes to RTC Alarm 2 Register 13 1 read-only WPNDCR1MIR Pending status of posted writes to RTC Control 1 Register 12 1 read-only WSYNCALM2MIR Synchronization status of posted writes to RTC Alarm 2 Register 15 1 read-only WSYNCCR1MIR Synchronization status of posted writes to RTC Control 1 Register 14 1 read-only SR3 RTC Status 3 0x48 16 read-write n 0x0 0x0 ALMINTMIR Read-only mirror of the ALMINT interrupt source in RTC Status 0 Register, acting as RTCOC0IRQ 8 1 read-only RTCIC0IRQ Sticky Interrupt Source for the RTC Input Capture Channel 0 0 1 read-write RTCIC2IRQ Sticky Interrupt Source for the RTC Input Capture Channel 2 2 1 read-write RTCIC3IRQ Sticky Interrupt Source for the RTC Input Capture Channel 3 3 1 read-write RTCIC4IRQ Sticky Interrupt Source for the RTC Input Capture Channel 4 4 1 read-write RTCOC1IRQ Sticky Interrupt Source for Output Compare Channel 1 9 1 read-write SR4 RTC Status 4 0x80 16 read-write n 0x0 0x0 RSYNCIC0 Synchronization status of posted reads of RTC Input Channel 0 10 1 read-only RSYNCIC2 Synchronization status of posted reads of RTC Input Channel 2 12 1 read-only RSYNCIC3 Synchronization status of posted reads of RTC Input Channel 3 13 1 read-only RSYNCIC4 Synchronization status of posted reads of RTC Input Channel 4 14 1 read-only WSYNCCR2IC Synchronization status of posted writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WSYNCCR3OC Synchronization status of posted writes to RTC Control 3 for Configuring Output Compare Channel Register 2 1 read-only WSYNCCR4OC Synchronization status of posted writes to RTC Control 4 for Configuring Output Compare Channel Register 3 1 read-only WSYNCOC1 Synchronization status of posted writes to RTC Output Compare Channel 1 Register 6 1 read-only WSYNCOC1ARL Synchronization status of posted writes to RTC Auto-Reload for Output Compare Channel 1 Register 5 1 read-only WSYNCOCMSK Synchronization status of posted writes to RTC Masks for Output Compare Channel Register 4 1 read-only WSYNCSR3 Synchronization status of posted clearances to interrupt sources in RTC Status 3 Register 0 1 read-only SR5 RTC Status 5 0x84 16 read-write n 0x0 0x0 RPENDIC0 Pending status of posted reads of RTC Input Channel 0 10 1 read-only RPENDIC2 Pending status of posted reads of RTC Input Channel 2 12 1 read-only RPENDIC3 Pending status of posted reads of RTC Input Channel 3 13 1 read-only RPENDIC4 Pending status of posted reads of RTC Input Channel 4 14 1 read-only WPENDCR2IC Pending status of posted writes to RTC Control 2 for Configuring Input Capture Channels Register 1 1 read-only WPENDCR3OC Pending status of posted writes to RTC Control 3 for Configuring Output Compare Channel Register 2 1 read-only WPENDCR4OC Pending status of posted writes to RTC Control 4 for Configuring Output Compare Channel Register 3 1 read-only WPENDOC1 Pending status of posted writes to Output Compare Channel 1 6 1 read-only WPENDOC1ARL Pending status of posted writes to RTC Auto-Reload for Output Compare Channel 1 Register 5 1 read-only WPENDOCMSK Pending status of posted writes to RTC Masks for Output Compare Channel Register 4 1 read-only WPNDSR0 Pending status of posted clearances of interrupt sources in RTC Status 3 Register 0 1 read-only SR6 RTC Status 6 0x88 16 read-write n 0x0 0x0 RTCFRZCNTPTR Pointer for the triple-read sequence of the RTC Freeze Count MMR 9 2 read-only RTCIC0SNAP Confirmation that RTC Snapshot 0, 1, 2 registers reflect the value of RTC Input Capture Channel 0 8 1 read-only RTCIC0UNR Sticky unread status of the RTC Input Capture Channel 0 0 1 read-only RTCIC2UNR Sticky unread status of the RTC Input Capture Channel 2 2 1 read-only RTCIC3UNR Sticky unread status of the RTC Input Capture Channel 3 3 1 read-only RTCIC4UNR Sticky unread status of the RTC Input Capture Channel 4 4 1 read-only TRM RTC Trim 0x1C 16 read-write n 0x0 0x0 ADD Trim Polarity 3 1 read-write IVL Trim interval in prescaled RTC time units 4 2 read-write IVL2EXPMIN Minimum power-of-two interval of prescaled RTC time units, which RTC Trim Register can select 6 4 read-write VALUE Trim value in prescaled RTC time units to be added or subtracted from the RTC count at the end of a periodic interval selected by RTC Trim Register 0 3 read-write SPI0 Serial Peripheral Interface SPI0 0x0 0x0 0x100 registers n SPI0_EVT Event 15 CNT Transfer byte count 0x18 16 read-write n 0x0 0x0 FRAMECONT Continue frame 15 1 read-write VALUE Transfer byte count 0 14 read-write CS_CTL Chip-Select control for multi-slave connections 0x30 16 read-write n 0x0 0x0 SEL Chip-Select control 0 4 read-write CS_OVERRIDE Chip-Select Override 0x34 16 read-write n 0x0 0x0 CTL CS Override Control 0 2 read-write CTL SPI configuration 1 0x10 16 read-write n 0x0 0x0 CON Continuous transfer enable 11 1 read-write CPHA Serial clock phase mode 2 1 read-write CPOL Serial Clock Polarity 3 1 read-write CSRST Reset Mode for CS Error bit 14 1 read-write LOOPBACK Loopback enable 10 1 read-write LSB LSB first transfer enable 5 1 read-write MASEN Master mode enable 1 1 read-write OEN Slave MISO output enable 9 1 read-write RFLUSH SPI Rx FIFO Flush enable 12 1 read-write RXOF RX overflow overwrite enable 8 1 read-write SPIEN SPI enable 0 1 read-write TFLUSH SPI Tx FIFO Flush enable 13 1 read-write TIM SPI transfer and interrupt mode 6 1 read-write WOM SPI Wired Or mode 4 1 read-write ZEN Transmit zeros enable 7 1 read-write DIV SPI baud rate selection 0xC 16 read-write n 0x0 0x0 VALUE SPI clock divider 0 6 read-write DMA SPI DMA enable 0x1C 16 read-write n 0x0 0x0 EN Enable DMA for data transfer 0 1 read-write RXEN Enable receive DMA request 2 1 read-write TXEN Enable transmit DMA request 1 1 read-write FIFO_STAT FIFO Status 0x20 16 read-write n 0x0 0x0 RX SPI Rx FIFO status 8 4 read-only TX SPI Tx FIFO status 0 4 read-only FLOW_CTL Flow Control 0x28 16 read-write n 0x0 0x0 MODE Flow control mode 0 2 read-write RDBURSTSZ Read data burst size minus 1 8 4 read-write RDYPOL Polarity of RDY/MISO line 4 1 read-write IEN SPI configuration 2 0x14 16 read-write n 0x0 0x0 CS Enable interrupt on every CS edge in slave CON mode 8 1 read-write IRQMODE SPI IRQ mode bits 0 3 read-write RDY Ready signal edge interrupt enable 11 1 read-write RXOVR Rx-overflow interrupt enable 10 1 read-write TXDONE SPI transmit done interrupt enable 12 1 read-write TXEMPTY Tx-FIFO Empty interrupt enable 14 1 read-write TXUNDR Tx-underflow interrupt enable 9 1 read-write XFRDONE SPI transfer completion interrupt enable 13 1 read-write RD_CTL Read Control 0x24 16 read-write n 0x0 0x0 CMDEN Read command enable 0 1 read-write OVERLAP Tx/Rx Overlap mode 1 1 read-write THREEPIN Three pin SPI mode 8 1 read-write TXBYTES Transmit byte count minus 1 for read command 2 4 read-write RX Receive 0x4 16 read-write n 0x0 0x0 BYTE1 8-bit receive buffer 0 8 read-only BYTE2 8-bit receive buffer, used only in DMA modes 8 8 read-only STAT Status 0x0 16 read-write n 0x0 0x0 CS CS Status 11 1 read-only CSERR Detected a CS error condition in slave mode 12 1 read-only CSFALL Detected a falling edge on CS, in slave CON mode 13 1 read-only CSRISE Detected a rising edge on CS, in slave CON mode 14 1 read-only IRQ SPI Interrupt status 0 1 read-only RDY Detected an edge on Ready indicator for flow-control 15 1 read-only RXIRQ SPI Rx IRQ 6 1 read-only RXOVR SPI Rx FIFO overflow 7 1 read-only TXDONE SPI Tx Done in read command mode 3 1 read-only TXEMPTY SPI Tx FIFO empty interrupt 2 1 read-only TXIRQ SPI Tx IRQ 5 1 read-only TXUNDR SPI Tx FIFO underflow 4 1 read-only XFRDONE SPI transfer completion 1 1 read-only TX Transmit 0x8 16 read-write n 0x0 0x0 BYTE1 8-bit transmit buffer 0 8 write-only BYTE2 8-bit transmit buffer, used only in DMA modes 8 8 write-only WAIT_TMR Wait timer for flow control 0x2C 16 read-write n 0x0 0x0 VALUE Wait timer for flow-control 0 16 read-write SPI2 Serial Peripheral Interface SPI0 0x0 0x0 0x100 registers n CNT Transfer byte count 0x18 16 read-write n 0x0 0x0 FRAMECONT Continue frame 15 1 read-write VALUE Transfer byte count 0 14 read-write CS_CTL Chip-Select control for multi-slave connections 0x30 16 read-write n 0x0 0x0 SEL Chip-Select control 0 4 read-write CS_OVERRIDE Chip-Select Override 0x34 16 read-write n 0x0 0x0 CTL CS Override Control 0 2 read-write CTL SPI configuration 1 0x10 16 read-write n 0x0 0x0 CON Continuous transfer enable 11 1 read-write CPHA Serial clock phase mode 2 1 read-write CPOL Serial Clock Polarity 3 1 read-write CSRST Reset Mode for CS Error bit 14 1 read-write LOOPBACK Loopback enable 10 1 read-write LSB LSB first transfer enable 5 1 read-write MASEN Master mode enable 1 1 read-write OEN Slave MISO output enable 9 1 read-write RFLUSH SPI Rx FIFO Flush enable 12 1 read-write RXOF RX overflow overwrite enable 8 1 read-write SPIEN SPI enable 0 1 read-write TFLUSH SPI Tx FIFO Flush enable 13 1 read-write TIM SPI transfer and interrupt mode 6 1 read-write WOM SPI Wired Or mode 4 1 read-write ZEN Transmit zeros enable 7 1 read-write DIV SPI baud rate selection 0xC 16 read-write n 0x0 0x0 VALUE SPI clock divider 0 6 read-write DMA SPI DMA enable 0x1C 16 read-write n 0x0 0x0 EN Enable DMA for data transfer 0 1 read-write RXEN Enable receive DMA request 2 1 read-write TXEN Enable transmit DMA request 1 1 read-write FIFO_STAT FIFO Status 0x20 16 read-write n 0x0 0x0 RX SPI Rx FIFO status 8 4 read-only TX SPI Tx FIFO status 0 4 read-only FLOW_CTL Flow Control 0x28 16 read-write n 0x0 0x0 MODE Flow control mode 0 2 read-write RDBURSTSZ Read data burst size minus 1 8 4 read-write RDYPOL Polarity of RDY/MISO line 4 1 read-write IEN SPI configuration 2 0x14 16 read-write n 0x0 0x0 CS Enable interrupt on every CS edge in slave CON mode 8 1 read-write IRQMODE SPI IRQ mode bits 0 3 read-write RDY Ready signal edge interrupt enable 11 1 read-write RXOVR Rx-overflow interrupt enable 10 1 read-write TXDONE SPI transmit done interrupt enable 12 1 read-write TXEMPTY Tx-FIFO Empty interrupt enable 14 1 read-write TXUNDR Tx-underflow interrupt enable 9 1 read-write XFRDONE SPI transfer completion interrupt enable 13 1 read-write RD_CTL Read Control 0x24 16 read-write n 0x0 0x0 CMDEN Read command enable 0 1 read-write OVERLAP Tx/Rx Overlap mode 1 1 read-write THREEPIN Three pin SPI mode 8 1 read-write TXBYTES Transmit byte count minus 1 for read command 2 4 read-write RX Receive 0x4 16 read-write n 0x0 0x0 BYTE1 8-bit receive buffer 0 8 read-only BYTE2 8-bit receive buffer, used only in DMA modes 8 8 read-only STAT Status 0x0 16 read-write n 0x0 0x0 CS CS Status 11 1 read-only CSERR Detected a CS error condition in slave mode 12 1 read-only CSFALL Detected a falling edge on CS, in slave CON mode 13 1 read-only CSRISE Detected a rising edge on CS, in slave CON mode 14 1 read-only IRQ SPI Interrupt status 0 1 read-only RDY Detected an edge on Ready indicator for flow-control 15 1 read-only RXIRQ SPI Rx IRQ 6 1 read-only RXOVR SPI Rx FIFO overflow 7 1 read-only TXDONE SPI Tx Done in read command mode 3 1 read-only TXEMPTY SPI Tx FIFO empty interrupt 2 1 read-only TXIRQ SPI Tx IRQ 5 1 read-only TXUNDR SPI Tx FIFO underflow 4 1 read-only XFRDONE SPI transfer completion 1 1 read-only TX Transmit 0x8 16 read-write n 0x0 0x0 BYTE1 8-bit transmit buffer 0 8 write-only BYTE2 8-bit transmit buffer, used only in DMA modes 8 8 write-only WAIT_TMR Wait timer for flow control 0x2C 16 read-write n 0x0 0x0 VALUE Wait timer for flow-control 0 16 read-write SYS System Identification and Debug Enable SYS 0x0 0x0 0x2C registers n SYS_GPIO_INTA GPIO Interrupt A 9 SYS_GPIO_INTB GPIO Interrupt B 10 ADIID ADI Identification 0x20 16 read-write n 0x0 0x0 VALUE Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part 0 16 read-only CHIPID Chip Identifier 0x24 16 read-write n 0x0 0x0 PARTID Part identifier 4 12 read-only REV Silicon revision 0 4 read-only SWDEN Serial Wire Debug Enable 0x40 16 read-write n 0x0 0x0 VALUE To enable SWD interface 0 16 write-only TMR0 General Purpose Timer TMR0 0x0 0x0 0x40 registers n TMR0_EVT Event 11 ACURCNT 16-bit timer value, asynchronous 0x18 16 read-write n 0x0 0x0 VALUE Counter value 0 16 read-only ALOAD 16-bit load value, asynchronous 0x14 16 read-write n 0x0 0x0 VALUE Load value, asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0x0 VALUE 16-bit captured value 0 16 read-only CLRINT Clear Interrupt 0xC 16 read-write n 0x0 0x0 EVTCAPT Clear captured event interrupt 1 1 write-only TIMEOUT Clear timeout interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0x0 0x0 CLK Clock select 5 2 read-write EN Timer enable 4 1 read-write EVTEN Event select 13 1 read-write EVTRANGE Event select range 8 5 read-write MODE Timer mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload control 7 1 read-write RSTEN Counter and prescale reset enable 14 1 read-write SYNCBYP Synchronization bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit timer value 0x4 16 read-write n 0x0 0x0 VALUE Current count 0 16 read-only LOAD 16-bit load value 0x0 16 read-write n 0x0 0x0 VALUE Load value 0 16 read-write PWMCTL PWM Control Register 0x20 16 read-write n 0x0 0x0 IDLESTATE PWM Idle State 1 1 read-write MATCH PWM Match enabled 0 1 read-write PWMMATCH PWM Match Value 0x24 16 read-write n 0x0 0x0 VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0x0 BUSY Timer Busy 6 1 read-only CAPTURE Capture event pending 1 1 read-only CNTRST Counter reset occurring 8 1 read-only PDOK Clear Interrupt Register synchronization 7 1 read-only TIMEOUT Timeout event occurred 0 1 read-only TMR1 General Purpose Timer TMR0 0x0 0x0 0x40 registers n TMR1_EVT Event 12 ACURCNT 16-bit timer value, asynchronous 0x18 16 read-write n 0x0 0x0 VALUE Counter value 0 16 read-only ALOAD 16-bit load value, asynchronous 0x14 16 read-write n 0x0 0x0 VALUE Load value, asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0x0 VALUE 16-bit captured value 0 16 read-only CLRINT Clear Interrupt 0xC 16 read-write n 0x0 0x0 EVTCAPT Clear captured event interrupt 1 1 write-only TIMEOUT Clear timeout interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0x0 0x0 CLK Clock select 5 2 read-write EN Timer enable 4 1 read-write EVTEN Event select 13 1 read-write EVTRANGE Event select range 8 5 read-write MODE Timer mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload control 7 1 read-write RSTEN Counter and prescale reset enable 14 1 read-write SYNCBYP Synchronization bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit timer value 0x4 16 read-write n 0x0 0x0 VALUE Current count 0 16 read-only LOAD 16-bit load value 0x0 16 read-write n 0x0 0x0 VALUE Load value 0 16 read-write PWMCTL PWM Control Register 0x20 16 read-write n 0x0 0x0 IDLESTATE PWM Idle State 1 1 read-write MATCH PWM Match enabled 0 1 read-write PWMMATCH PWM Match Value 0x24 16 read-write n 0x0 0x0 VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0x0 BUSY Timer Busy 6 1 read-only CAPTURE Capture event pending 1 1 read-only CNTRST Counter reset occurring 8 1 read-only PDOK Clear Interrupt Register synchronization 7 1 read-only TIMEOUT Timeout event occurred 0 1 read-only TMR2 General Purpose Timer TMR0 0x0 0x0 0x40 registers n TMR2_EVT Event 40 ACURCNT 16-bit timer value, asynchronous 0x18 16 read-write n 0x0 0x0 VALUE Counter value 0 16 read-only ALOAD 16-bit load value, asynchronous 0x14 16 read-write n 0x0 0x0 VALUE Load value, asynchronous 0 16 read-write CAPTURE Capture 0x10 16 read-write n 0x0 0x0 VALUE 16-bit captured value 0 16 read-only CLRINT Clear Interrupt 0xC 16 read-write n 0x0 0x0 EVTCAPT Clear captured event interrupt 1 1 write-only TIMEOUT Clear timeout interrupt 0 1 write-only CTL Control 0x8 16 read-write n 0x0 0x0 CLK Clock select 5 2 read-write EN Timer enable 4 1 read-write EVTEN Event select 13 1 read-write EVTRANGE Event select range 8 5 read-write MODE Timer mode 3 1 read-write PRE Prescaler 0 2 read-write RLD Reload control 7 1 read-write RSTEN Counter and prescale reset enable 14 1 read-write SYNCBYP Synchronization bypass 15 1 read-write UP Count up 2 1 read-write CURCNT 16-bit timer value 0x4 16 read-write n 0x0 0x0 VALUE Current count 0 16 read-only LOAD 16-bit load value 0x0 16 read-write n 0x0 0x0 VALUE Load value 0 16 read-write PWMCTL PWM Control Register 0x20 16 read-write n 0x0 0x0 IDLESTATE PWM Idle State 1 1 read-write MATCH PWM Match enabled 0 1 read-write PWMMATCH PWM Match Value 0x24 16 read-write n 0x0 0x0 VALUE PWM Match Value 0 16 read-write STAT Status 0x1C 16 read-write n 0x0 0x0 BUSY Timer Busy 6 1 read-only CAPTURE Capture event pending 1 1 read-only CNTRST Counter reset occurring 8 1 read-only PDOK Clear Interrupt Register synchronization 7 1 read-only TIMEOUT Timeout event occurred 0 1 read-only UART0 Unknown UART0 0x0 0x0 0x100 registers n UART_EVT Event 14 COMACR Auto Baud Control 0x40 16 read-write n 0x0 0x0 ABE Auto Baud enable 0 1 read-write DNIEN enable done interrupt 1 1 read-write EEC Ending Edge Count 8 4 read-write SEC Starting Edge Count 4 3 read-write TOIEN enable time-out interrupt 2 1 read-write COMASRH Auto Baud Status (High) 0x48 16 read-write n 0x0 0x0 CNT CNT[19:12] Auto Baud Counter value 0 8 read-only COMASRL Auto Baud Status (Low) 0x44 16 read-write n 0x0 0x0 BRKTO Timed out due to long time break condition 1 1 read-only CNT CNT[11:0] Auto Baud Counter value 4 12 read-only DONE Auto Baud Done successfully 0 1 read-only NEETO Timed out due to no valid ending edge found 3 1 read-only NSETO Timed out due to no valid start edge found 2 1 read-only COMCTL UART control register 0x30 16 read-write n 0x0 0x0 ForceClkOn Force UCLKg on 1 1 read-write REV UART revision ID 8 8 read-only RXINV invert receiver line 4 1 read-write EN000 don't invert receiver line (idling high) 0 EN001 invert receiver line (idling low) 1 COMDIV Baudrate divider 0x28 16 read-write n 0x0 0x0 DIV Baud rate divider 0 16 read-write COMFBR Fractional Baud Rate 0x24 16 read-write n 0x0 0x0 DIVM Fractional baud rate M divide bits 1 to 3 11 2 read-write DIVN Fractional baud rate N divide bits 0 to 2047. 0 11 read-write FBEN Fractional baud rate generator enable 15 1 read-write COMFCR FIFO Control 0x20 16 read-write n 0x0 0x0 FDMAMD FIFO DMA mode 3 1 read-write MODE0 in DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to 0 MODE1 in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full 1 FIFOEN FIFO enable as to work in 16550 mode 0 1 read-write RFCLR clear RX FIFO 1 1 write-only RFTRIG RX FIFO Trig level 6 2 read-write TFCLR clear TX FIFO 2 1 write-only COMIEN Interrupt Enable 0x4 16 read-write n 0x0 0x0 EDMAR DMA requests in receive mode 5 1 read-write EDMAT DMA requests in transmit mode 4 1 read-write EDSSI Modem status interrupt 3 1 read-write ELSI Rx status interrupt 2 1 read-write ERBFI Receive buffer full interrupt 0 1 read-write ETBEI Transmit buffer empty interrupt 1 1 read-write COMIIR Interrupt ID 0x8 16 read-write n 0x0 0x0 FEND FIFO enabled 6 2 read-only NIRQ Interrupt flag 0 1 read-only STA Interrupt status 1 3 read-only COMLCR Line Control 0xC 16 read-write n 0x0 0x0 BRK Set Break 6 1 read-write EPS Parity Select 4 1 read-write PEN Parity Enable 3 1 read-write SP Stick Parity 5 1 read-write STOP Stop Bit 2 1 read-write WLS Word Length Select 0 2 read-write COMLCR2 second Line Control 0x2C 16 read-write n 0x0 0x0 OSR Over Sample Rate 0 2 read-write COMLSR Line Status 0x14 16 read-write n 0x0 0x0 BI Break Indicator 4 1 read-only DR Data Ready 0 1 read-only FE Framing Error 3 1 read-only FIFOERR data byte(s) in RX FIFO have either parity error, frame error or break indication. only used in 16550 mode Read-clear if no more error in RX FIFO 7 1 read-only OE Overrun Error 1 1 read-only PE Parity Error 2 1 read-only TEMT COMTX and Shift Register Empty Status 6 1 read-only THRE COMTX Empty 5 1 read-only COMMCR Modem Control 0x10 16 read-write n 0x0 0x0 DTR Data Terminal Ready 0 1 read-write LOOPBACK Loopback mode 4 1 read-write OUT1 Output 1 2 1 read-write OUT2 Output 2 3 1 read-write RTS Request to send 1 1 read-write COMMSR Modem Status 0x18 16 read-write n 0x0 0x0 CTS Clear To Send 4 1 read-only DCD Data Carrier Detect 7 1 read-only DCTS Delta CTS 0 1 read-only DDCD Delta DCD 3 1 read-only DDSR Delta DSR 1 1 read-only DSR Data Set Ready 5 1 read-only RI Ring Indicator 6 1 read-only TERI Trailing Edge RI 2 1 read-only COMRFC RX FIFO byte count 0x34 16 read-write n 0x0 0x0 RFC Current RX FIFO data bytes 0 5 read-only COMRSC RS485 half-duplex Control 0x3C 16 read-write n 0x0 0x0 DISRX disable RX when transmitting 2 1 read-write DISTX Hold off TX when receiving 3 1 read-write OENP SOUT_EN polarity 0 1 read-write OENSP SOUT_EN de-assert before full stop bit(s) 1 1 read-write COMRX Receive Buffer Register 0x0 16 read-write n 0x0 0x0 RBR Receive Buffer Register 0 8 read-only COMSCR Scratch buffer 0x1C 16 read-write n 0x0 0x0 SCR Scratch 0 8 read-write COMTFC TX FIFO byte count 0x38 16 read-write n 0x0 0x0 TFC Current TX FIFO data bytes 0 5 read-only COMTX Transmit Holding Register COMRX 0x0 16 read-write n 0x0 0x0 THR Transmit Holding Register 0 8 write-only WDT0 Watchdog Timer WDT0 0x0 0x0 0x20 registers n WDT_EXP Digital Die Watchdog 5 CCNT Current count value 0x4 16 read-write n 0x0 0x0 VALUE Current count value 0 16 read-only CTL Control 0x8 16 read-write n 0x0 0x0 EN Timer enable 5 1 read-write IRQ Timer interrupt 1 1 read-write MODE Timer mode 6 1 read-write PRE Prescaler 2 2 read-write div1 source clock/1. 0 div16 source clock/16. 1 div256 source clock/256 (default). 2 Reserved Reserved 3 SPARE Unused spare bit 7 1 read-write LOAD Load value 0x0 16 read-write n 0x0 0x0 VALUE Load value 0 16 read-write RESTART Clear interrupt 0xC 16 read-write n 0x0 0x0 CLRWORD Clear watchdog 0 16 write-only STAT Status 0x18 16 read-write n 0x0 0x0 CLRIRQ Clear Interrupt Register write sync in progress 1 1 read-only COUNTING Control Register write sync in progress 3 1 read-only IRQ WDT Interrupt 0 1 read-only LOADING Load Register write sync in progress 2 1 read-only LOCKED Lock status bit 4 1 read-only RSTCTL Reset Control Register written and locked 5 1 read-only XINT0 External interrupt configuration XINT0 0x0 0x0 0x50 registers n XINT_EVT1 External Wakeup Interrupt n 2 AFE_EVT3 AFE Interrupt 4 CFG0 External Interrupt Configuration 0x0 32 read-write n 0x0 0x0 IRQ0EN External Interrupt 0 Enable bit 3 1 read-write IRQ0MDE External Interrupt 0 Mode registers 0 3 read-write IRQ1EN External Interrupt 1 Enable bit 7 1 read-write IRQ1MDE External Interrupt 1 Mode registers 4 3 read-write IRQ2EN External Interrupt 2 Enable bit 11 1 read-write IRQ2MDE External Interrupt 2 Mode registers 8 3 read-write IRQ3EN External Interrupt 3 enable bit 15 1 read-write IRQ3MDE External Interrupt 3 Mode registers 12 3 read-write UART_RX_EN External Interrupt enable bit 20 1 read-write UART_RX_MDE External Interrupt using UART_RX wakeup Mode registers 21 3 read-write CLR External Interrupt Clear 0x10 32 read-write n 0x0 0x0 IRQ0 External interrupt 0 0 1 read-write IRQ1 External interrupt 1 1 1 read-write IRQ2 External interrupt 2 2 1 read-write IRQ3 External interrupt 3 3 1 read-write UART_RX_CLR External interrupt Clear for UART_RX WAKEUP interrupt 5 1 read-write EXT_STAT External Wakeup Interrupt Status 0x4 32 read-write n 0x0 0x0 STAT_EXTINT0 Interrupt status bit for External Interrupt 0 0 1 read-only STAT_EXTINT1 Interrupt status bit for External Interrupt 1 1 1 read-only STAT_EXTINT2 Interrupt status bit for External Interrupt 2 2 1 read-only STAT_EXTINT3 Interrupt status bit for External Interrupt 3 3 1 read-only STAT_UART_RXWKUP Interrupt status bit for UART RX wakeup interrupt 5 1 read-only NMICLR Non-Maskable Interrupt Clear 0x14 32 read-write n 0x0 0x0 CLR NMI clear 0 1 read-write